可配置时间窗口的低功耗CNN/SNN混合硬件加速器设计

李琪康; 张跃军; 王黎勋; 张会红; 汪鹏君; 谢微; 苏斌杰

doi:10.11999/JEIT260926

可配置时间窗口的低功耗CNN/SNN混合硬件加速器设计

doi: 10.11999/JEIT260926 cstr: 32379.14.JEIT260926

1.
宁波大学集成电路学院宁波 315211
2.
温州大学电气与电子工程学院温州 325035
3.
宁波市海曙区人民医院心内科宁波 315211

基金项目: 宁波市科创甬江2035重点研发计划(2024Z139)，慈溪市重点研发专项(CZ2025006)，宁波大学“双一流”合作专项方向委托科技合作项目(HX2024000574, HX2025000106)，宁波市卫生健康科技计划项目(2024Y27, 2025Y26)

详细信息

作者简介:
李琪康：男，博士生，高效深度神经网络加速器设计，　2401100057@nbu.edu.cn

张跃军：男，教授，低功耗、高信息密度集成电路理论和设计，　zhangyuejun@nbu.edu.cn

王黎勋：男，博士生，低功耗存算一体电路设计及实现

张会红：女，副教授，控制理论与应用、低功耗集成电路理论与优化设计

汪鹏君：男，教授，研究方向为集成电路设计、信息安全等技术及其相关理论

谢微：女，硕士研究生，研究方向心血管内科

苏斌杰：男，心血管内科主任医师，研究方向心血管内科

通讯作者:
张跃军　zhangyuejun@nbu.edu.cn

中图分类号: TN403
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出版历程
- 修回日期: 2026-10-16
- 录用日期: 2026-10-16
- 网络出版日期: 2026-10-29

A Low-Power CNN/SNN Hybrid Hardware Accelerator with Configurable Time-Window Architecture

1.
School of Integrated Circuit, Ningbo University, Ningbo 315211, China
2.
College of Electrical and Electronic Engineering, Wenzhou University, Wenzhou, Zhejiang 325035, China
3.
Department of Cardiology, Haishu District People’s Hospital, Ningbo 315211, China

Funds: The Key R&D Program of Cixi (CZ2025006), the Ningbo University “Double First-Class” Cooperation Special Directional Entrusted Scientific and Technological Cooperation Project under Grant (HX2024000574, HX2025000106) and Ningbo Municipal Health and Healthcare Science Technology Programme Projects (2024Y27, 2025Y26)

摘要

摘要: 近年来，融合卷积神经网络(Convolutional Neural Networks, CNN)与脉冲神经网络(Spiking Neural Network, SNN)的脉冲卷积神经网络加速器在边缘智能中展现出显著优势。然而，现有设计多采用固定时间窗口(Time Windows, TW)执行积分迭代，难以适配不同任务的时序复杂度。本文提出一种基于可配置TW的低功耗混合硬件加速器架构。首先，基于不同任务的时空复杂度分析，提出可配置TW自定义指令集，减少推理延迟与计算开销；其次，构建支持零跳跃的数据复用计算阵列，并引入CNN/SNN多模式算子统一映射，提升计算资源利用率；最后，提出事件驱动执行机制与细粒度时钟门控策略，减少计算过程与数据传输过程中无效操作和冗余访存。在TSMC 28 nm工艺实现CNN/SNN混合加速器，芯片核心面积为0.75 mm²。在0.81 V供电电压和100 MHz工作频率下，该加速器面向MIT-BIH、N-TIDIGITS、N-MNIST、IMAGE-100和UniMiB SHAR等多类任务实现75.3%–98.4%的识别精度，最低单次推理能耗仅为147.78 nJ。与相关工作比较，所提出的可配置TW机制在保证识别精度的同时，可实现1.24×–30×的能耗降低，显著提升系统能效。
- 可配置时间窗口 /
- 脉冲神经网络 /
- RISC-V /
- 硬件加速器
Abstract: In recent years, hybrid convolutional neural network (CNN) and spiking neural network (SNN) accelerators have shown great potential for edge intelligence. However, existing designs typically employ fixed time windows (TW) for temporal integration, limiting their adaptability to tasks with different temporal complexities. This work presents a low-power hybrid CNN/SNN accelerator with configurable TWs. First, a configurable TW instruction set is developed based on the spatiotemporal complexity of different tasks to reduce inference latency and computational overhead. Second, a zero-skipping data-reuse processing array with unified CNN/SNN operator mapping is designed to improve computational resource utilization. Finally, an event-driven execution scheme and fine-grained clock-gating strategy are introduced to eliminate redundant operations and memory accesses during computation and data transfer. The proposed CNN/SNN accelerator is fabricated in a 28-nm TSMC CMOS process, occupying a core area of 0.75 mm². At 0.81 V and 100 MHz, it achieves classification accuracies ranging from 75.3% to 98.4% across MIT-BIH, N-TIDIGITS, N-MNIST, IMAGE-100, and UniMiB SHAR, with a minimum energy consumption of 147.78 nJ per inference. Compared with prior works, the configurable-TW mechanism reduces energy consumption by 1.24×–7.6× while maintaining competitive classification accuracy, significantly improving the overall energy efficiency. Objective The goal of this work is to design an efficient and low-power CNN/SNN hybrid neuromorphic SoC based on the RISC-V architecture, addressing the limitations of conventional SNN hardware with fixed TW under different task requirements. By introducing a configurable TW mechanism, the temporal integration length can be flexibly adjusted according to task complexity, thereby reducing redundant time-step computations and lowering inference latency and energy consumption. Methods To address the varying time-window requirements of different tasks, this work presents a RISC-V-based SCNN processor with a configurable TW. First, a custom instruction set is developed to configure the TW threshold of the underlying hardware according to the complexity of input samples, enabling demand-driven computation while reducing inference latency and computational overhead. Second, a zero-skipping data-reuse processing array is designed to improve computational resource utilization. Finally, an event-driven execution mechanism and fine-grained clock-gating strategy are introduced to eliminate redundant operations and unnecessary memory accesses during computation and data transfer. The chip is fabricated in a 28-nm TSMC CMOS process with a core area of 0.75 mm². Across MIT-BIH, N-TIDIGITS, N-MNIST, IMAGE-100, and UniMiB SHAR tasks, the accelerator achieves classification accuracies ranging from 75.3% to 98.4%, with a minimum energy consumption of 147.78 nJ per inference. Results and Discussions Experimental results validate the effectiveness of the proposed configurable-TW SCNN processor under diverse workloads. Cross-task analysis (Fig. 7) shows that accuracy generally improves with increasing TW, but sensitivity varies significantly across tasks. Event-driven datasets such as N-MNIST and UniMiB SHAR exhibit strong temporal redundancy, achieving near-saturated accuracy (97.8%–98.4%) at small TW (≥3), whereas temporally dependent tasks like N-TIDIGITS require larger TW to maintain performance, indicating that TW demand is inherently data-modality dependent. Single-task evaluation (Fig. 8 and Fig. 9) further demonstrates that reducing TW can significantly lower spike rates and computational cost with negligible accuracy degradation. The latency–accuracy trade-off (Fig. 10) reveals that blindly increasing TW leads to exponential growth in addition operations and inference latency without proportional accuracy gains. The optimal TW varies across tasks, highlighting the necessity of dynamic TW adaptation. Conclusions This work presents a hybrid hardware accelerator with a configurable TW. By dynamically adjusting the TW, the proposed design addresses the performance and energy-efficiency limitations of fixed temporal resolution in conventional SNN hardware. Implemented in a TSMC 28-nm process, the accelerator occupies a core area of only 0.75 mm² and supports multimodal tasks, including physiological-signal, speech, visual, and activity recognition. It achieves classification accuracies of 75.3%–98.4% and a minimum energy consumption of 147.78 nJ per inference. Compared with fixed-TW designs, the proposed accelerator offers greater task adaptability, computational efficiency, and energy efficiency, reducing energy consumption by 1.24×–7.6× under the same process technology.
- Configurable time window /
- Spiking neural network /
- RISC-V /
- Hardware accelerator

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图 1 分类样本TW尺寸对分类准确性的影响

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图 2 基于可配置TW的CNN/SNN芯片架构

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图 3 卷积阵列与映射数据流

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图 4 LIF神经元硬件电路设计

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图 5 SCNN指令计算调度流

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图 6 TSMC 28nm芯片信息

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图 7 不同时间窗口下对于不同检测任务的准确率影响

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图 8 在N-MNIST数据集下不同时间窗口对于准确率与发射率影响

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图 9 在N-MNIST数据集下不同分类的准确率影响

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图 10 不同时间窗口的推理延迟与准确率的关系

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表 1 与相关文献比较结果

参考	文献[13]	文献[14]	文献[15]	文献[16]	文献[17]	文献[18]	本文
工艺	28 nm	40 nm	28 nm	28 nm	28 nm	40 nm	28 nm
芯片面积	1.25 mm²	0.66 mm²	0.45 mm²	10.24 mm²	14.44 mm²	0.738 mm²	0.75 mm²
频率	40 MHz	30-130 MHz	13-115 MHz	100 MHz	300 MHz	30 MHz	100 MHz
内存	266.5 KB	66 KB	138 KB	1711 KB	3.3 MB	40 KB	64 KB
网络类型	SNN	SNN	SRNN	SNN	SNN	SNN	SCNN
位宽 (bits)	8 bit	4 bit	8 bit	4 bit	8 bit	8 bit	8/4 bit
数据集	N-MNIST N-TIDIGIT IBM DVS Gesture	MIT-BIH MNIST N-MNIST	IBM DVS Gesture Spiking Heidelberg Digits Delayed cue integration	MNIST N-MNIST Gesture	MNIST CIFAR10	MIT-BIH ETH-80 MNIST	MIT-BIH N-TIDIGIT N-MNIST UniMiB SHAR IMAGE-100
网络架构	1024-512-10	ECG: 96-80-40 -5 IMAGE: 256-128-10 IMAGE-A: 384-128-10	256-256-16	N/A	N/A	N/A	ECG:c16-c32-c32-fc32-5 KWS:c32-c128-f64-11 IMAGE-A:c32-c32-f64-10 HAR:c32-c64-c64-f64-9 CIFAR-100: Resnet-18
准确率	IMAGE-A:96% KWS:92.6% Gesture:92%	ECG:97.12% IMAGE:97.26% IMAGE-A:96.08%	Gesture: 87.3% KWS:90.7% Nav:96.4%	MNIST:99.2% N-MNIST:98.2% Gesture:94.3%	MNIST: 99.48% CIFAR10: 93.52%	ECG:89.8% Object:94.2% IMAGE: 81.8%	ECG:97.6% KWS:94.5% IMAGE-A:98.4% HAR:98.28% IMAGE-B: 75.3%
分类/ 能效	IMAGE-A: 343 nJ KWS: 6.1 μJ Gesture:3.9 μJ	ECG:42.57 nJ IMAGE:146.8 nJ IMAGE-A: 194.6nJ	Gesture:46.1 μJ KWS: 4.4 μJ Nav:1.4 μJ	IMAGE:0.91mJ IMAGE-A: 2.1mJ Gesture:3.6mJ	MNIST:76.6 μJ CIFAR10: 4.2mJ	ECG:97.7 nJ Object:6.3μJ IMAGE: 27.35 μJ	ECG:147.78 nJ KWS: 202.54 nJ IMAGE-A:276.33 nJ HAR: 1.41 μJ IMAGE-B: 155 μJ

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