A Review of Energy-Efficient Superconducting Computing Architectures
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摘要: 随着摩尔定律和登纳德定律的演进日趋放缓，速度与功耗日益成为制约算力持续提升的根本瓶颈。除了延续半导体工艺演进与体系结构优化来实现能效的持续提升之外，发展与当前半导体技术形成互补的新型电路技术尤为迫切。作为一种新型低温计算技术，超导计算技术正成为一种极具吸引力的半导体互补方案，有望满足未来计算系统对算力及能效的要求。凭借其在速度与能效方面的显著优势，超导计算技术正日益受到关注，相关研究投入不断增加，为实现大规模超导计算以及推动其实际应用奠定了基础。本文对超导计算领域在体系结构方面的进展进行了梳理。根据其内部运行原理，本文将超导计算架构大致分为三大类：传统计算架构、超导神经形态计算和超导量子计算，分别讨论了各类架构的优势与局限性，并进一步探讨了超导计算架构领域面临的主要挑战及未来发展方向。Abstract:
Significance The slowing of Moore’s law and the end of Dennard scaling have made power consumption a fundamental constraint on the continued growth of computing capability. Although improvements in semiconductor fabrication and conventional architectures remain important, complementary technologies are increasingly needed to meet the performance and energy requirements of future computing systems. Superconducting computing offers a promising approach through Josephson junction devices, extremely short switching times, and low switching energies. Single flux quantum (SFQ) circuits are a class of superconducting circuits that encode information in discrete voltage pulses. Among superconducting logic families, rapid single-flux-quantum (RSFQ) logic can achieve orders-of-magnitude higher operating frequencies than conventional complementary metal-oxide-semiconductor (CMOS) technology, whereas adiabatic quantum-flux-parametron (AQFP) logic enables ultralow power dissipation approaching the thermodynamic limit through adiabatic switching. Translating these device advantages into practical systems, however, requires architectures that accommodate pulse encoding, clock synchronization, restricted fanout, and limited memory density. This review examines architectural developments in superconducting computing and organizes them into conventional computing architectures, superconducting neuromorphic computing, and superconducting quantum computing. It distinguishes their physical mechanisms and evaluation criteria while identifying connections through common devices, fabrication capabilities, design constraints, and the demand for efficient cryogenic control electronics. Progress The review first introduces representative superconducting logic families and their circuit characteristics, emphasizing the effects of clocking, path balancing, and fanout constraints on architectural design. Typical superconducting digital circuits require deep pipelines, additional storage elements to synchronize converging paths, and splitter networks to distribute signals. These requirements influence circuit area, operating frequency, and achievable throughput, making the direct adoption of CMOS architectures inadequate. Within conventional computing, the review traces the development of microprocessors, arithmetic logic units, multipliers, register files, and branch predictors. Bit-serial, bit-parallel, and bit-slice architectures provide different tradeoffs between hardware complexity and performance. Early processors primarily established functional feasibility, whereas recent designs address pipeline inefficiency, storage density, and synchronization. Alternating logic elements, compact storage cells, and improved clocking schemes illustrate the shift toward architectural optimization. Representative examples include the CORE processor family and the AQFP-based MANA processor, while SuperCore and SuperSFQ illustrate attempts to exploit wider parallel execution at high frequencies. For neural computation, JBNN, SuperNPU, SMART, and JBSA demonstrate how precision reduction, storage organization, and execution style can be adapted to superconducting logic. Their comparisons emphasize that peak device speed alone cannot determine application performance. Specialized accelerators are examined through neural network inference and cryptographic computation. Binary neural networks reduce precision requirements and hardware complexity, making them attractive under current fabrication constraints. AQFP implementations combine low-energy logic with in-memory computation, while stochastic computing exploits device behavior to simplify arithmetic. For deeper neural networks, superconducting accelerators benefit from regular dataflow and high operating frequencies, but sequential access in shift register memories can substantially limit utilization. Heterogeneous scratchpad memories and bit-serial execution alleviate access and bandwidth constraints through coordinated changes to storage organization, processing elements, and scheduling. Representative graph convolutional network accelerators further demonstrate the potential of algorithm and hardware co-design. Cryptographic designs cover SHA-256 hashing, Advanced Encryption Standard encryption, and number-theoretic transforms (NTTs) for post-quantum cryptography (PQC). These studies show opportunities for high-throughput and low-energy consumption, but also expose the area costs of fully unrolled pipelines, the limitations imposed by feedback paths, and the need for dense storage. Reported energy advantages are interpreted with attention to whether refrigeration costs are included. Reconfigurable computing is reviewed through superconducting field-programmable gate arrays (SFPGAs), including designs using nondestructive readout cells, magnetic Josephson junctions, and hybrid memories. Existing efforts demonstrate programmable logic and interconnection structures, but remain largely at the circuit level. The review also discusses dual clocking, multiphase clocking, and temporal logic. These approaches reduce path balancing overhead or encode information in pulse arrival times, offering alternatives to conventional Boolean architectures while introducing tradeoffs involving throughput, synchronization, and implementation complexity. For neuromorphic computing, superconducting neuron designs are classified according to current, charge, flux, and digital representations of membrane potential. Current-based neurons use Josephson junction thresholds to reproduce firing behavior, charge-based neurons exploit quantum phase-slip junctions, and flux-based neurons accumulate magnetic flux in inductive elements. Digital designs implement neuronal and synaptic functions with standard superconducting logic cells. Analog implementations reproduce neuronal dynamics through device behavior, whereas discrete and digital approaches seek improved robustness and compatibility with established superconducting cell libraries. Despite their potential, analog neurons often require application-specific customization and remain sensitive to noise and fabrication variations. The review examines neuron and synapse structures, representative spiking neural network implementations, and comparisons of performance and energy efficiency with CMOS designs. Network expansion is constrained by high fan-in and fan-out requirements, interconnection overhead, timing alignment, and sensitivity to device parameters. Mutual inductive coupling, merger-based signal collection, and splitter trees provide different implementation options, each with limitations in scalability and applicability. For quantum computing, the review introduces representative superconducting Qubits and focuses on Transmon design. It summarizes progress toward larger processors and discusses differences in coherence, control, fabrication, and scalability. The review distinguishes Qubit characteristics from controller integration requirements. Quantum controllers are examined alongside Qubits because increasing processor size intensifies wiring and thermal constraints between room-temperature equipment and cryogenic devices. Cryogenic CMOS and SFQ control provide alternative integration paths. SFQ pulse sequences support Qubit manipulation, while Josephson photomultipliers (JPMs) enable cryogenic Qubit readout and facilitate integration with SFQ digital logic, potentially reducing the complexity of conventional microwave readout chains. Nevertheless, large-scale integrated superconducting control systems remain less mature than individual circuit demonstrations. Conclusions Superconducting computing has progressed from device demonstrations toward increasingly systematic architectural exploration. Its high-frequency operation and low switching energy offer opportunities for conventional computing, neuromorphic systems, and quantum control. These advantages do not automatically produce comparable system benefits, because memory organization, pipeline structure, interconnection, fabrication, and refrigeration determine practical efficiency. Four major obstacles are identified. First, limited fabrication density, yield, and reliability hinder the realization of larger and more complex chips. Second, immature cryogenic memory technologies force processors to rely on area-intensive shift registers or hybrid interfaces that introduce additional latency and power costs. Third, electronic design automation (EDA) tools do not yet provide a sufficiently complete and scalable flow for superconducting circuits, particularly for sequential logic, feedback structures, and physical design. Fourth, quantum system integration faces increasing wiring density, heat dissipation, and crosstalk as Qubit counts grow. Progress therefore requires coordinated optimization across devices, circuits, architectures, and cryogenic systems, together with careful distinctions between simulated performance, fabricated demonstrations, and system performance. Prospects Future research should prioritize five directions. First, superconducting design automation should support sequential synthesis, verification, feedback handling, and scalable physical implementation through consistent data models and interfaces. Second, high-density memories based on flux storage, nanowires, or other emerging mechanisms should be explored alongside hybrid integration of Josephson-junction and CMOS technologies. Such efforts should address both processor memory bottlenecks and the integration of quantum control electronics. Third, superconducting reconfigurable architectures require standardized benchmarks and evaluation methods that quantify area, speed, and power, enabling comparisons beyond isolated circuit demonstrations and encouraging alternatives to conventional island-style organizations. Fourth, scalable superconducting spiking neural networks should combine efficient neuron and synapse designs with network topology optimization, practical routing, time-division multiplexing, and pruning. Fifth, quantum computing requires coordinated design of Qubit chips, cryogenic controllers, room-temperature instrumentation, and refrigeration systems to balance fidelity, connectivity, coherence, and system power. Addressing these directions will help establish the conditions under which superconducting technologies can deliver practical advantages and support their development from laboratory prototypes into useful computing systems. -
图 3 实现逻辑函数“$ \mathrm{q}=\mathrm{a}\wedge \mathrm{b}\wedge \mathrm{c} $”的RSFQ门级电路图和时序波形
表 1 RSFQ逻辑、AQFP逻辑与CMOS电路对比
电路特性 RSFQ AQFP CMOS 有源器件 约瑟夫森结 约瑟夫森结 晶体管 无源器件 电感 电感 电容 信息载体 SFQ电压脉冲 电流脉冲 电平信号 时钟机制 流时钟 多相时钟 零偏差时钟 扇出能力 1($ \gt 1 $时需使用
分流器)1($ \gt 1 $时需使用
分流器)$ \gt $1 供电方式 DC AC DC 互连线 微带线 微带线 金属线 开关功耗 $ \times {10}^{-19} $ J $ \times {10}^{-21} $ J $ \times {10}^{-15} $ J 典型频率 $ 50 $ GHz $ 5 $ GHz $ 4 $ GHz 
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表 2 不同超导微处理器、ALU、乘法器、寄存器文件及分支预测器设计
方案 年份 SFQ逻辑 局部频率 (GHz) 字长/规格 JJ数量 功耗 (mW) 架构类型 微处理器 FLUX-1[24] 2002 RSFQ 20 8 65759 14～15 比特并行 CORE1α6[26] 2005 RSFQ 18 8 6319 2.10 比特串行 SCRAM2[29] 2007 RSFQ 20 8 8197 2.61 比特串行 CORE1γ[28] 2008 RSFQ 25 8 22302 6.56 比特串行 CORE e4[30] 2016 RSFQ 80 8 7194 2.03 比特串行 CORE e2h[31] 2017 RSFQ 50 8 N/A N/A 比特串行 SFQ-GLP1[32] 2020 RSFQ 32 4 23713 6.50 比特并行 [33] 2020 RSFQ 16.70 8 7702 N/A 比特并行 MANA[34] 2021 AQFP 5 4 21460 N/A 比特并行 SuperCore[35] 2024 ERSFQ 40 32 778086 2.60 比特并行 SuperSFQ[36] 2025 ERSFQ 34 32 1045000 N/A 比特并行 ALU [37] 2015 RSFQ 80 8 1555 N/A 比特串行 [38] 2016 RSFQ 50 4 3481 N/A 比特切片 [39] 2018 RSFQ N/A 16 5784 N/A 比特切片 [40] 2019 ERSFQ 10 8 6840 N/A 比特并行 [41] 2021 xSFQ 22.22 8 2800 N/A 比特并行 乘法器 [42] 2013 RSFQ 20 8×8 5948 1.70 比特并行 [43] 2015 RSFQ 50 24×24 N/A N/A 比特串行 [44] 2017 RSFQ 50 32×32 56885 N/A 比特切片 寄存器文件 [45] 2022 RSFQ 18.87 32×32 16133 3.91 比特并行 分支预测器 [46] 2023 RSFQ N/A 128×32 225874 48.34 比特并行
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表 3 超导神经网络加速器代表性工作对比
加速器类型 架构 逻辑类型 主频(GHz) 功耗
(mW)性能优势 能效优势 二值神经网络
推理加速器JBNN[2] CMOS@300K 1.20 17.19 对比77K CMOS：
$ \uparrow $71×对比77K CMOS：
$ \uparrow $929×(不含制冷)CMOS@77K 2.24 12.03 RSFQ/ERSFQ 50 9.78 (ERSFQ) IBM ReRAM[63] CMOS@300K 0.10 12.50 ×1 (参考基准) ×1 SupeRBNN[54] AQFP 5 6.20×10–3
～7.60×10–3对比ReRAM：
$ \uparrow $36.50×对比ReRAM：
$ \uparrow $(7.80×104)×(不含制冷)深度神经网络
推理加速器Google TPU[65] CMOS@300K 0.70 4×104 ×1 ×1 SuperNPU[55] RSFQ/ERSFQ 52.60 1.90×103 (ERSFQ) 对比TPU：
$ \uparrow $23×对比TPU：
$ \uparrow $490×(不含制冷)Smart[56] RSFQ/ERSFQ 52.60 N/A 对比SuperNPU：
$ \uparrow $2.20×～3.9×对比SuperNPU：
能耗$ \downarrow $71%～86%(不含制冷)JBSA[57] RSFQ/ERSFQ 23.30 N/A 对比SuperNPU：
$ \uparrow $11%对比SuperNPU：
$ \uparrow $2.30×(不含制冷)图卷积网络
加速器GCN加速器[64] AQFP 5 N/A 对比FPGA方案：
$ \uparrow $3.34×～5.22×对比FPGA：$ \uparrow $(1.07×104～8.68×104)×
(含制冷)
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表 4 现有的超导神经元和突触设计方案
文献 膜电位表征
类型神经元胞体类型 突触设计 峰值性能
(SOPS)能效
(SOPS/W)对比CMOS基准
(TrueNorth[95])验证级别 [88] 电流 模拟，可偏置调节 模拟，定制不可调 N/A N/A N/A 仿真 [89] 电流 模拟，可偏置调节 数字，数字可调 $ 1.20\times {10}^{10} $ $ 8.57\times {10}^{11} $(不含制冷) 能效：$ \uparrow 2.14\times $ 流片 [90] 电荷 准数字，定制不可调 模拟，外磁场调节 N/A N/A N/A 仿真 [91] 电荷 准数字，定制不可调 模拟，外磁场调节 N/A $ 4.30\times 10{^{1}}{^{9}} $
(不含制冷)能效：$ \uparrow (1.08\times {10}^{8})\times $ 仿真 [92] 磁通 准数字，可偏置调节 数字，数字可调 $ 1.78\times {10}^{11} $
($ 32\times 32 $网络)$ 5.03\times {10}^{12} $
(不含制冷)能效：$ \uparrow 12.58\times $ 仿真 [93] 磁通 准数字，数字可调 N/A N/A N/A N/A 仿真 [94] 数字 数字，数字可调 数字，数字可调 $ 1.36\times {10}^{12} $
($ 16\times 16 $网络)$ 3.24\times {10}^{13} $
(不含制冷)能效：$ \uparrow 81\times $ 流片
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表 5 国内外通用门式超导Transmon量子芯片或原型机核心指标对比
研究机构 代表芯片或原型机 物理比特数 双比特门保真度 相干时间 ($ \text{μs} $) Google Willow (2024)[107] 105 $ \gt 99\% $(平均) T1=68, T2=89(平均) IBM Heron r3 (2025)[111] 156 $ \gt 99\% $(中位数) T2=350(平均) 中国科学技术大学 “祖冲之三号” (2025)[108] 105 $ 99.62\% $(平均) T1=72, T2=58(平均) 浙江大学 “天目2号” (2025)[112] 125 $ 99.50\% $(中位数) N/A Rigetti Cepheus-1-108Q (2026)[113] 107 $ 98.82\% $(中位数) T1=29, T2=11(中位数) 本源量子 “本源悟空-180” (2026)[110] 180 $ 99.00\% $(平均) T1=40, T2=20(平均)
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