从门到电路元：功能感知划分驱动的层次化电路表示学习

叶聚阳; 陈麒麟; 王耀华

doi:10.11999/JEIT260645

从门到电路元：功能感知划分驱动的层次化电路表示学习

doi: 10.11999/JEIT260645 cstr: 32379.14.JEIT260645

计算机学院国防科技大学长沙 410073

详细信息

作者简介:
叶聚阳：男，硕士生，研究方向为电子设计自动化，邮箱　yejuyang@nudt.edu.cn

陈麒麟：男，博士生，研究方向为电子设计自动化

王耀华：男，博士，研究方向为计算机体系结构，邮箱　yhwang@nudt.edu.cn

通讯作者:
王耀华　yhwang@nudt.edu.cn (通信和一作均需唯一)

中图分类号: TP18
计量
- 文章访问数: 7
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- 被引次数: 0
出版历程
- 修回日期: 2026-08-10
- 录用日期: 2026-08-10
- 网络出版日期: 2026-08-12

Function-Aware Partitioning Driven Hierarchical Circuit Representation Learning

College of Computer Science and Technology, National University of Defense Technology, Changsha 410073, China

摘要

摘要: 从大规模门级网表中学习高质量电路表示是将机器学习技术应用于电子设计自动化的核心挑战之一。随着数字集成电路规模的跃升，现有基于图Transformer的方法因计算与内存开销过高而难以扩展。为此，该文提出一种功能感知划分驱动的层次化电路表示学习框架。该框架受大语言模型分词机制启发，提出以功能独立性比率(FIR)为优化目标将大规模网表划分为功能内聚的电路元作为表示学习的基本单元。在此基础上，该文设计二阶段自监督预训练框架以适配电路元级表示学习。第一阶段通过掩码自编码器与边预测学习电路元级全局表示；第二阶段在冻结电路元嵌入的条件下，通过布尔等价变换驱动的对比学习算法，学习具有全局上下文感知的门级判别性表示。在多个从小规模到超大规模电路上的实验表明，基于FIR的划分相较当前最佳方案提升超过24%，在下游全电路功能识别与门级功能识别任务中，该文方法在所有可比较数据集上均显著优于当前最先进方法，且是唯一可扩展至BOOM(8.12M门)与OpenC910(22.3M门)的方案。
- 电路表示学习 /
- 超图划分 /
- 自监督预训练 /
- Graph Transformer
Abstract: Objective One of the core challenges in applying machine learning techniques to electronic design automation (EDA) lies in learning high-quality circuit representations from large-scale gate-level netlists. As modern digital integrated circuits scale to tens of millions of gates, existing methods based on graph neural networks (GNNs) and graph transformers (GTs) suffer from excessive computational and memory overhead, rendering them impractical for industrial-scale designs. The fundamental issue is the lack of a proper tokenization mechanism for netlists—unlike natural language, where subword tokenization effectively compresses long sequences, the circuit domain lacks an analogous decomposition strategy that preserves functional semantics while reducing the effective graph size. This work aims to bridge this gap by introducing a hypergraph-partitioning-based circuit tokenizer that decomposes massive netlists into functionally cohesive sub-circuits, termed circuit elements, thereby enabling scalable and fine-grained representation learning. Methods This paper proposes a function-aware hypergraph partitioning driven framework for large-scale circuit representation learning. Inspired by the tokenization paradigm of large language models, the framework first models a gate-level netlist as a directed hypergraph, where gates are nodes and signals are hyperedges that can connect multiple gates. A novel optimization objective, the Functional Independence Ratio (FIR), is introduced to guide the partitioning process. FIR incorporates circuit structural priors and a bus recognition correction mechanism that identifies bus-structured signals based on structural similarity (gate type purity across predecessor/successor levels) and spatial similarity (topological distance variance within candidate groups). The bus recognition module corrects the effective interface count, ensuring that functionally cohesive modules are not penalized for using wide buses. An iterative greedy refinement procedure accepts only moves that strictly decrease FIR, converging to a locally optimal partition. On top of the partitioned circuit elements, a two-stage self-supervised pretraining framework is designed. In the first stage, a masked autoencoder with edge prediction tasks is applied to the coarse-grained circuit-element graph, learning global inter-element dependencies. The graph transformer encoder is then frozen and circuit element embeddings are saved. In the second stage, within each circuit element, a contrastive learning scheme is employed at the gate level. Positive pairs are constructed via Boolean equivalence transformations (e.g., associativity, De Morgan's laws), which preserve the Boolean function while altering the gate-level structure. Negative pairs are drawn from functionally different circuit elements within the same batch. The training jointly optimizes node-level and local-global alignment losses. A feature-wise modulation mechanism injects circuit-element-level context into gate-level representations, enabling the same gate type to acquire different embeddings depending on its functional context. Results and Discussions Extensive experiments are conducted on circuits collected from multiple sources, including ITC99, EPFL, OpenCores, and three RISC-V SoC designs (Rocket, BOOM, and OpenC910), with the largest design containing 22.3 million gates. For the tokenizer evaluation, FIR-based partitioning is compared against Mt-kahypar using the Adjusted Mutual Information (AMI) and Adjusted Rand Index (ARI) metrics, with the original module hierarchy serving as ground truth. Across all three RISC-V designs, FIR achieves AMI improvements of 24.6% to 27.1% and ARI improvements of 25.5% to 35.8% over Mt-kahypar, demonstrating consistent and substantial gains in functional coherence. On downstream tasks, the proposed method consistently outperforms state-of-the-art baselines including DeepGate4 and NetTAG across all comparable datasets. For full-circuit function recognition, the proposed method achieves F1 scores of 0.896, 0.861, 0.817, and 0.773 on ITC99, EPFL, OpenCores, and Rocket, respectively, representing improvements of 10.0% to 15.4% over the strongest baseline. Crucially, on BOOM (8.12M gates) and OpenC910 (22.3M gates), the proposed method is the only approach capable of completing training without running out of memory, achieving F1 scores of 0.771 and 0.748 for full-circuit tasks and 0.723 and 0.679 for gate-level tasks, respectively. Ablation studies with six model variants reveal a clear division of labor: the module-level pretraining stage dominates full-circuit performance (20.9% F1 drop when removed), while the gate-level pretraining stage dominates gate-level performance (26.1% F1 drop when removed). The FIR partitioning objective contributes 8.6% and 11.7% F1 improvements at the full-circuit and gate levels, respectively. The bus recognition module and the two-stage architecture also show consistent positive contributions across all metrics. Conclusions This paper presents a novel framework that addresses the scalability challenge in circuit representation learning by introducing a function-aware hypergraph partitioning tokenizer and a two-stage self-supervised pretraining architecture. The key insight is that by abstracting the intermediate circuit element level between individual gates and the full circuit, one can achieve both scalability to multi-million-gate designs and fine-grained gate-level discriminative capability. The proposed FIR objective effectively captures functional cohesion during partitioning, and the two-stage pretraining framework decouples global context learning from local representation refinement. Experimental results demonstrate state-of-the-art performance on function recognition tasks and, more importantly, the unique ability to scale to industrial-sized designs where existing methods fail. Future work includes extending the framework to other EDA tasks such as logic synthesis and physical design, exploring more aggressive hierarchical strategies for billion-gate designs, and adapting the bus recognition mechanism to non-standard cell libraries.
- Circuit Representation Learning /
- Hypergraph Partitioning /
- Self-Supervised Pretraining /
- Graph Transformer

HTML全文

图 1 功能感知划分驱动的层次化电路表示学习概览

下载: 全尺寸图片幻灯片

图 2 译码器总线识别

下载: 全尺寸图片幻灯片

图 3 二阶段自监督预训练框架

下载: 全尺寸图片幻灯片

图 4 消融实验结果

下载: 全尺寸图片幻灯片

表 1 电路元、模块与子图概念区分

概念	定义	来源
电路元	超图划分产生的划分块，本文中间抽象	FIR引导的超图划分
模块	设计者定义的功能块	原始设计层次(真值标签)
子图	电路元内部平展门级有向图	电路元内部连接关系

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表 2 5种综合策略

综合策略	时钟频率(MHz)	扇出限制	库	展平综合
默认	100	无	GTECH	否
默认	300	无	ICsprout	是
面积优先	300	50	ICsprout	是
时序优先	300	无	ICsprout	否
时序优先	800	50	ICsprout	是

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表 3 不同划分方法在三个RISC-VSoC网表上的AMI/ARI/时间对比

划分方法	Rocket			BOOM			OpenC910
划分方法	AMI	ARI	时间(s)	AMI	ARI	时间(s)	AMI	ARI	时间(s)
Mt-kahypar	0.593	0.580	12.4	0.591	0.554	187.3	0.575	0.538	521.6
hMetis+FIR	0.653	0.609	10.5	0.637	0.605	169.8	0.631	0.613	494.2
FM+FIR	0.663	0.625	10.3	0.621	0.622	158.4	0.616	0.611	487.5
Mt-kahypar+FIR	0.755	0.744	13.1	0.741	0.692	198.5	0.715	0.721	553.0

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表 4 Mt-kahypar+FIR划分后电路元规模统计

电路	总门数	电路元数	最大规模	最小规模	标准差
Rocket	5.99×10⁵	774	1135	381	191.4
BOOM	8.12×10⁶	2849	4016	1319	682.1
OpenC910	2.23×10⁷	4722	6527	2768	903.5

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表 5 全电路功能识别表现

(a) 全电路功能识别——准确率
方法	ITC99	EPFL	OpenCores	Rocket	BOOM	OpenC910
DeepGate4	0.827	0.794	0.746	0.710	Out of memory
NetTAG	0.792	0.801	0.721	0.708	Out of memory
Ours	0.897	0.872	0.822	0.795	0.781	0.743
(b) 全电路功能识别——召回率
方法	ITC99	EPFL	OpenCores	Rocket	BOOM	OpenC910
DeepGate4	0.801	0.772	0.724	0.693	Out of memory
NetTAG	0.821	0.766	0.715	0.670	Out of memory
Ours	0.895	0.850	0.813	0.752	0.761	0.754
(c) 全电路功能识别——F1分数
方法	ITC99	EPFL	OpenCores	Rocket	BOOM	OpenC910
DeepGate4	0.814	0.783	0.735	0.701	Out of memory
NetTAG	0.806	0.782	0.718	0.688	Out of memory
Ours	0.896	0.861	0.817	0.773	0.771	0.748

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表 6 门级功能识别表现

(a)门级功能识别——准确率
方法	ITC99	EPFL	OpenCores	Rocket	BOOM	OpenC910
DeepGate4	0.776	0.745	0.696	0.667	0.594	0.433
NetTAG	0.758	0.691	0.692	0.671	0.611	0.446
Ours	0.850	0.848	0.813	0.750	0.735	0.672
(b) 门级功能识别——召回率
方法	ITC99	EPFL	OpenCores	Rocket	BOOM	OpenC910
DeepGate4	0.751	0.720	0.677	0.642	0.613	0.485
NetTAG	0.715	0.721	0.680	0.611	0.603	0.494
Ours	0.865	0.822	0.784	0.756	0.712	0.687
(c) 门级功能识别——F1分数
方法	ITC99	EPFL	OpenCores	Rocket	BOOM	OpenC910
DeepGate4	0.763	0.732	0.686	0.654	0.603	0.458
NetTAG	0.736	0.706	0.686	0.640	0.607	0.469
Ours	0.857	0.835	0.798	0.753	0.723	0.679

下载: 导出CSV

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