面向边缘时序推理的逐通道单门循环单元及其忆阻器电路实现

齐浩明; 韩俊涛; 蒲向荣; 李梓豪; 张章

doi:10.11999/JEIT260630

面向边缘时序推理的逐通道单门循环单元及其忆阻器电路实现

doi: 10.11999/JEIT260630 cstr: 32379.14.JEIT260630

合肥工业大学，微电子学院合肥 230601

基金项目: 安徽省自然科学基金(2308085MF207)

详细信息

作者简介:
齐浩明：男，硕士生，研究方向为神经形态电路

韩俊涛：男，博士生，研究方向为忆阻神经网络电路

蒲向荣：男，博士生，研究方向为忆阻神经网络及存算一体电路设计

李梓豪：男，硕士生，研究方向为存算一体电路

张章：男，教授，研究方向为混合信号芯片及基于混合器件的AI神经形态芯片

通讯作者:
张章　zhangzhang@hfut.edu.cn

中图分类号: TP389; TN43
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出版历程
- 收稿日期: 2026-05-15
- 修回日期: 2026-07-24
- 录用日期: 2026-09-30
- 网络出版日期: 2026-10-13

Point-Wise Single-Gate Recurrent Unit for Edge Temporal Inference and Its Memristor-Based In-Memory Computing Circuit Implementation

School of Microelectronics, Hefei University of Technology, Hefei 230601, China

Funds: Natural Science Foundation of Anhui Province (2308085MF207)

摘要

摘要: 近年来，边缘设备对时序信息实时处理的需求持续增长。门控循环神经网络具有较强的序列建模能力，已广泛应用于相关任务，但其复杂的递归连接、较高的存储开销以及时间步内的串行计算依赖，制约了其在资源受限边缘系统中的高效部署。为此，本文提出了逐通道单门循环单元 P-SGRU，以逐通道递归调制替代传统全连接隐状态到隐状态(hidden-to-hidden，H2H)变换，将递归参数复杂度由二次形式降低为线性形式，从结构上压缩递归路径规模。实验结果表明，在相同网络维度下，相较于 LSTM 和 GRU，P-SGRU的H2H 递归参数量分别减少约 98.44% 和 97.92%。P-SGRU进一步通过解除保持系数分支与候选隐状态分支之间的串行依赖，提高了时间步内计算并行性。基于 40 nm 工艺的电路评估结果显示，其单时间步更新关键路径延时较GRU降低约66.1%，降低了边缘时序推理中的时间步内延时开销。为进一步提升P-SGRU在边缘硬件中的实现效率，本文设计了基于忆阻器的存内计算电路，以协同降低边缘时序推理中的存储、功耗和延时开销。部署后的 P-SGRU 电路在 Row-wise MNIST、IMDB和UCI HAR任务上的分类准确率分别达到 95.03%、86.76%和89.46%，相较于软件模型的最大准确率损失仅为0.02%。进一步的非理想性实验表明，在静态电导偏差和动态读噪声共同作用下，三项分类任务的准确率最大下降0.133%，所设计电路在测试范围内保持了较稳定的分类推理性能。
- 忆阻器 /
- 循环神经网络(RNN) /
- 逐通道单门循环单元(P-SGRU) /
- 存内计算 /
- 边缘时序推理
Abstract: Objective With the rapid development of edge intelligence, wearable electronics, and Internet-of-Things applications, edge devices increasingly require low-latency and low-power temporal inference under limited storage and hardware resources. Gated recurrent neural networks, such as Long Short-Term Memory (LSTM) and Gated Recurrent Unit (GRU), provide strong sequence modeling capability, but their dense hidden-to-hidden transformations introduce considerable parameter storage and vector-matrix multiplication overhead. In addition, the serial dependency between gate-related computation and candidate hidden-state computation increases the intra-step recurrent delay, which limits their efficient deployment in resource-constrained edge systems. Memristor-based in-memory computing can reduce data movement and accelerate vector-matrix operations, but directly mapping conventional gated recurrent structures onto memristor circuits still suffers from complex recurrent paths and peripheral circuit overhead. Therefore, a recurrent structure that jointly considers lightweight recurrence, intra-step parallelism, and hardware implementation efficiency is needed. To address this issue, this paper proposes a Point-Wise Single-Gate Recurrent Unit (P-SGRU) and a corresponding memristor-based in-memory computing circuit for efficient edge temporal inference.Methods P-SGRU is designed to simplify the recurrent path of conventional gated recurrent units. It replaces the fully connected hidden-to-hidden transformation with point-wise recurrent modulation, so that each hidden-state channel is recurrently modulated only by its corresponding channel at the previous time step. A single retention coefficient is introduced to control the fusion of the previous hidden state and the candidate hidden state. By removing the reset-gate-related dependency in GRU, the retention-coefficient branch and the candidate hidden-state branch can be computed in parallel within the same time step, thereby improving intra-step computational parallelism. According to the P-SGRU computation process, a memristor-based in-memory computing circuit is designed, consisting of a retention-coefficient computation unit, a candidate hidden-state computation unit, and a state update unit. Signed weights are represented by positive-negative differential memristor conductance arrays, and point-wise recurrent weights are mapped only to their corresponding channel positions. To reduce the mismatch between software training and circuit implementation, PWL activation-aware training is adopted, where PWL-Sigmoid and PWL-Tanh functions consistent with the circuit implementation are used during training. After training, the weights are quantized to 8 bits and mapped to memristor conductance states. The proposed model is evaluated on Adding Problem, Row-wise MNIST, IMDB, and UCI HAR. For UCI HAR, the original nine-channel smartphone inertial signals with 128 time steps are used to evaluate six-class human activity recognition in a realistic edge-sensing scenario. The corresponding memristor-based circuit is analyzed under a 40 nm process condition.Results and Discussions Compared with LSTM and GRU, the two-layer P-SGRU reduces the number of hidden-to-hidden recurrent parameters by 98.44% and 97.92%, respectively, and removes full hidden-to-hidden vector-matrix multiplication branches (Table 2). On the tested sequence tasks, P-SGRU-2L achieves 98.21%±0.20% accuracy on Row-wise MNIST and 86.85%±0.13% accuracy on IMDB, while the single-layer P-SGRU is selected for circuit implementation considering the model scale and circuit overhead of resource-constrained edge systems (Table 2). On UCI HAR, P-SGRU-2L achieves 91.87%±0.94% accuracy and 91.94%±0.94% macro-F1 with 10,246 parameters (Table 2). After being mapped to the proposed memristor-based circuit, the single-layer P-SGRU achieves circuit-level accuracies of 95.03%±0.06% and 86.76%±0.05% on Row-wise MNIST and IMDB, respectively, with a maximum accuracy loss of only 0.02% compared with the software model. Under the 40 nm process condition, the proposed P-SGRU circuit shows lower or comparable delay under different task configurations (Table 3). In addition, the single-channel, single-time-step update simulation shows that the critical-path delay is reduced from 524.5 ps in GRU to 177.9 ps in P-SGRU, corresponding to a 66.1% reduction, verifying the effect of removing the serial dependency between the retention-coefficient branch and the candidate hidden-state branch.Conclusions This paper addresses efficient temporal inference in resource-constrained edge systems by proposing P-SGRU and its memristor-based in-memory computing circuit implementation. The proposed P-SGRU replaces the fully connected hidden-to-hidden transformation with point-wise recurrent modulation, thereby reducing the parameter scale and computational complexity of the recurrent path. Meanwhile, by decoupling the retention-coefficient branch from the candidate hidden-state branch, P-SGRU improves intra-step computational parallelism and shortens the recurrent update path. Experimental results on Adding Problem, Row-wise MNIST, IMDB, and UCI HAR show that P-SGRU maintains favorable sequence modeling performance while significantly simplifying the recurrent structure. In particular, the UCI HAR results demonstrate that the stacked P-SGRU can effectively model real multi-channel inertial sequences while retaining a lower parameter count than conventional gated recurrent models. Circuit-level evaluation further demonstrates that the P-SGRU circuit after hardware mapping achieves inference results close to those of the software model, and the single-channel single-time-step update critical-path delay is reduced by about 66.1% compared with GRU under the 40 nm process condition. These results indicate that P-SGRU provides a lightweight and efficient algorithm-circuit co-design solution for edge temporal inference. Future work will further extend P-SGRU to more complex edge temporal tasks and explore its integration with high-density in-memory computing arrays and edge intelligence systems for low-power and low-latency temporal inference.
- Memristor /
- Recurrent Neural Network (RNN) /
- Point-Wise Single-Gate Recurrent Unit (P-SGRU) /
- In-Memory Computing /
- Edge Temporal Inference

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图 1 GRU和P-SGRU结构对比图

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图 2 忆阻器实测I–V特性及SPICE模型拟合结果

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图 3 基于忆阻器阵列的保持系数$ {\alpha }_{t} $硬件电路

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图 4 用于候选隐状态的PWL-Tanh激活电路

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图 5 状态更新单元电路

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图 6 静态电导偏差和动态读噪声对P-SGRU电路推理性能的影响

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表 1 SPICE模型主要参数表

参数	数值	参数	数值
$ I_{0}^{-} $	1.98×10^–12A	$ {m}^{+} $	2.85
$ I_{0}^{+} $	9.27×10^–10A	$ {A}^{-} $	5.26×10^–5
$ {I}_{0,\text{on}} $	6.32×10^–6A	$ {A}^{+} $	1.44×10^–4
$ I_{\text{cc}}^{-} $	2mA	$ {k}_{\text{set}} $	4.09
$ I_{\text{cc}}^{+} $	2.12mA	$ {k}_{\text{reset}} $	0.55
$ {V}_{\text{set}} $	0.86V	$ {\alpha }_{\text{s}} $	0.61
$ {V}_{\text{reset}} $	0.5V	$ {\alpha }_{\text{r}} $	0.29
$ G_{\text{off}}^{-} $	1.54×10^–5S	$ {\beta }_{\text{s}} $	1.32
$ G_{\text{off}}^{+} $	8.13×10^–6S	$ {\beta }_{\text{r}} $	1.63
$ {G}_{\text{on}} $	4.46×10^–3S	$ {x}_{0} $	5.61×10^–11
$ {m}^{-} $	2.36

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表 2 不同循环神经网络模型的复杂度与任务性能对比

模型	层数	H2H 参数量	H2H VMM 分支数	Adding Problem		Row-wise MNIST		IMDB		UCI HAR
模型	层数	H2H 参数量	H2H VMM 分支数	参数量	MSE (×10^–4)↓	参数量	准确率(%)↑	参数量	准确率(%)↑	参数量	准确率(%)↑
LSTM	1	16384	4	17473	7.53±6.01	32970	98.19±0.13	41666	86.64±0.27	19590	89.98±0.85
GRU	1	12288	3	13121	4.77±0.78	26954	98.37±0.11	33346	86.72±0.27	14790	90.04±0.49
SRU[18]	1	0	0	833	8.19±2.29	16330	94.56±0.12	20866	86.67±0.24	2886	87.97±0.32
MGU[8]	1	8192	2	8641	8.04±4.82	20810	98.38±0.14	24898	85.80±0.45	9862	89.87±0.75
IndRNN[9]	1	64	0	321	8.25±1.95	10826	91.42±0.27	12610	86.07±0.12	1094	82.90±1.52
P-SGRU	1	128	0	577	9.27±7.26	12746	95.35±0.14	16834	86.81±0.06	1798	88.92±0.55
P-SGRU	2	256	0	9025	5.42±0.48	21194	98.21±0.20	25282	86.85±0.13	10246	91.87±0.94

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表 3 本文电路与代表性循环神经网络硬件实现的性能对比

指标	本文	[16] TCAS-I 2025	[17] TED2022
工艺/器件	40 nm，忆阻器	0.45 μm，忆阻器	40 nm，忆阻器
网络结构	P-SGRU	GRU	GRU
评估范围	P-SGRU模块、P-SGRU完整推理链路	GRU 模块	GRU 单元电路
功耗 / mW	46.51(Adding Problem) 76.54(Row-wise MNIST) 317.25(IMDB)	25	173.65(MNIST)
延时/ns	39.90(Adding Problem) 5.59(Row-wise MNIST) 37.82(IMDB)	—	45(MNIST)
面积/$ \mu {m}^{2} $	234.3	302.472	6283.9

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