一种支持跨层信任闭环的指令驱动安全协处理器架构

王俊辉; 彭奕景; 刘家宏; 王耀华

doi:10.11999/JEIT260619

一种支持跨层信任闭环的指令驱动安全协处理器架构

doi: 10.11999/JEIT260619 cstr: 32379.14.JEIT260619

1.
国防科技大学计算机学院长沙 410073
2.
国防科技大学先进微处理器芯片与系统教育部重点实验室长沙 410073

详细信息

作者简介:
王俊辉：男，副研究员，研究方向为微处理器设计与芯片安全

彭奕景：男，博士生，研究方向为微处理器设计与芯片安全

刘家宏：男，博士生，研究方向为微处理器设计与芯片安全

王耀华：男，研究员，研究方向为微处理器设计与芯片安全

通讯作者:
彭奕景　pengyijing@nudt.edu.cn

中图分类号: TN47
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- 被引次数: 0
出版历程
- 收稿日期: 2026-05-15
- 修回日期: 2026-09-28
- 录用日期: 2026-10-16
- 网络出版日期: 2026-10-25

An Instruction-Based Secure Coprocessor Architecture for Cross-Layer Trust Closure

1.
College of Computer Science and Technology, National University of Defense Technology, Changsha 410073, China
2.
Key Laboratory of Advanced Microprocessor Chips and Systems(NUDT), Ministry of Education, Changsha 410073, China

摘要

摘要: 针对物联网设备安全防护中传统纯软件方案性能低且易受物理攻击，以及基于有限状态机(FSM)配置的硬件加速器存在状态爆炸、扩展困难及敏感数据易在总线暴露等问题，该文提出一种支持跨层信任闭环的指令驱动安全协处理器架构(IBSCA)。该架构摒弃传统FSM硬连线控制，引入精简指令集概念构建“译码-调度-执行”流水线，将PUF、Hash及加解密等异构算子抽象为可独立寻址的原子操作；通过指令驱动范式解耦控制与数据通路，赋予运行时动态编程能力以解决FSM状态爆炸问题；同时实现算子级细粒度编排与关键数据片上驻留，构建从物理信任源到数据加密的跨层硬件信任闭环，杜绝总线监听风险。基于FPGA的原型验证结果表明，该架构可正确支撑IoT场景复杂协议，相比传统FSM设计具备更高的协议扩展灵活性，为资源受限IoT终端提供了可靠的硬件安全底座。
- 安全协处理器 /
- 物联网 /
- 指令驱动 /
- 跨层信任闭环
Abstract: Objective With the rapid development of the Internet of Things, massive terminal devices deployed in physically open environments are highly vulnerable to physical probing, side-channel attacks, and bus sniffing. Current IoT security solutions exhibit significant limitations: software-based protocol implementations suffer from severe performance bottlenecks and lack physical protection, while dedicated hardware accelerators based on Finite State Machine (FSM) configurations experience state explosion, poor scalability, coarse control granularity, and the critical risk of sensitive data exposure on unprotected buses due to frequent data movement. Therefore, it is of great necessity and importance to construct an efficient, lightweight, and security-analyzable hardware protection system that supports fine-grained operator orchestration and cross-layer trust closure for resource-constrained IoT devices. Methods To address the aforementioned issues, an Instruction-Based Secure Coprocessor Architecture for Cross-Layer Trust Closure (IBSCA) is proposed. The architecture abandons the traditional FSM hard-wired control mode and introduces a Reduced Instruction Set Computer concept to construct a processor-like “Decode-Dispatch-Execute” pipeline. A dedicated 32-bit reduced instruction set architecture is defined, where all instructions are divided into five functional fields: Control Bits, Functional Unit Selection, Operand Addresses, Destination Address, and Reserved Bits. The Control Bits explicitly define data flow direction and operational attributes, where the source selection bit and result write-back bit are key to realizing the “data residency” security policy. The hardware microarchitecture consists of four core modules: Interface, Control Logic, Functional Unit, and Memory. The Interface Module serves as the sole communication channel to minimize the attack surface; the Control Logic Module dynamically generates micro-operation control signals; the Functional Unit Module integrates heterogeneous operators like PUF, ECC, and Hash; and the Memory Module guarantees data confidentiality through on-chip data residency. The execution flow comprises three coupled stages: instruction sequence generation, fetch and decode, and instruction execution. The host directly injects instruction streams via the standard bus, abstracting heterogeneous operators into independently addressable atomic operations to decouple control logic from data paths. Furthermore, a PUF-based lightweight WiFi authentication protocol is mapped into the IBSCA to verify the design. Results and Discussions Based on the FPGA platform, the IBSCA secure IP is implemented and evaluated. Functionally, waveform-level simulation verifies that when a PUF instruction is issued, the coprocessor accurately decodes it, activates the PUF module, and writes the response back to the on-chip register, explicitly demonstrating that sensitive data like PUF responses and keys reside and flow entirely within the chip (Fig. 4). End-to-end protocol tests are conducted by mapping the PUF-based WiFi authentication protocol into the IBSCA. The protocol steps are successfully translated into binary instruction sequences, executing continuously to output the correct Response and Session Key (Fig. 5). Performance evaluations indicate that the access latency of IBSCA is 6802 ns, which is 23.95% shorter than the software baseline (8944 ns) and only 12.2% longer than the FSM baseline (6062 ns) (Table 2). The slight latency gap compared to FSM stems from implementation details such as handshake bubbles rather than paradigm flaws. Resource overhead analysis shows that the IBSCA control module consumes only 800 LUTs and 1550 FFs, achieving a significant reduction of 67.8% and 57.8% respectively compared to the FSM control module (2483 LUTs and 3676 FFs), as its general scheduling logic absorbs complexity into instruction encoding rather than explicit state nodes. Furthermore, SAIF-annotated post-route power analysis (100% nets matched, high confidence) shows that, at the timing-verified 100 MHz clock, the total on-chip power of IBSCA is 0.365 W, of which the control module contributes only about 5 mW of dynamic power (4.1% of the total dynamic power). Conclusions An instruction-based secure coprocessor architecture for cross-layer trust closure is proposed to address the limitations of existing IoT security solutions. By introducing a reduced instruction set paradigm and constructing a processor-like pipeline, the architecture successfully decouples control logic from data paths, eliminating the FSM state explosion problem and providing runtime dynamic programming capabilities. The fine-grained orchestration of heterogeneous operators and the on-chip data residency mechanism ensure that sensitive data form a closed loop on-chip, constructing a robust hardware closed-loop trust chain from physical root of trust generation to runtime data encryption protection. FPGA prototype verification and resource analysis confirm that IBSCA achieves a superior balance among protocol extension flexibility, hardware resource overhead, and security performance, providing a flexible, efficient, and reliable hardware security foundation for resource-constrained IoT terminal devices.
- Secure coprocessor /
- Internet of things /
- Instruction-Driven /
- Cross-Layer trust closure

HTML全文

图 1 指令格式定义

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图 2 安全协处理器硬件微架构示意图

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图 3 IBSCA 调度流程

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图 4 WiFi协议模拟结果R3

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图 5 WiFi协议服务器验证结果

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1 控制逻辑模块核心实现

1 module control (
2 input [31:0] instr, // 　　指令字
3 input instr_vld, // 　　指令有效
4 input [255:0] data_in1, data_in2,
5 input [511:0] data_result, // 　　执行结果
6 input response, // 　　完成响应
7 output [5:0] src1, src2, dst, // 　　地址域
8 output [9:0] valid_signals, // 　　one-hot选通
9 output [511:0] data_out); // 　　操作数据
// (1) 译码站：并行提取指令字段(图1)
10 assign m_lo = instr[0]; // 　　源选择位
11 assign m_st = instr[1]; // 　　写回位
12 assign op_cnt = instr[4]; // 　　操作数数量
13 assign funct = instr[9:5]; // 　　功能单元选择
14 assign {dst, src2, src1} = instr[27:10];
// (2) 源数据站：按m_lo选源
15 always @(posedge clk) if (instr_vld) begin
16 {op2, op1} <= m_lo ?
17 {op_cnt ? data_in2 : 0, data_in1}
18: : result_reg; // 　　片内前递
19: data_vld <= 1; end // 　　就绪，交调度站
// (3) 调度站：译码funct与装载的数据汇合
20: always @(posedge clk)
21: if (data_vld && funct==Hash) begin
22: data_out <= {op2, op1}; // 　　组512位消息块
23: valid_signals[0] <= 1; end // 　　启动Hash
// 其余算子同理。各站间以op1/op2与data_vld寄存器分隔：功　能单元执行第i条指令时，译码站与源数据站可推进后续指令，　实现指令级并行与流水线重叠
// (4) 结果驻留站：m_st = 0时片内锁存
24: always @(posedge clk) if (response&&!m_st)
25: result_reg <= data_result; // 　　片内复用
26: endmodule

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2 基于PUF的轻量级WiFi认证算法

输入：C₁'，C₂'，C₃，R₂'，R₃'
输出：R_1new'，R_2new'，R_3new'，R₁'，H_client
1 R₃ ← P(C₃)　　// 由片上PUF生成响应
2 nonce ← R₃ $\oplus $ R₃'　　// 恢复会话随机数
3 C₂ ← C₂' $\oplus $ nonce
4 R₂ ← R₂' $\oplus $ nonce
5 if R₂ ≠ P(C₂) then　　// 设备端校验
6 　return 认证拒绝
7 end if
8 C₁ ← C₁' $\oplus $ nonce
9 R₁″ ← P(C₁)
10 R₁' ← nonce $\oplus $ R₁″
11 R_1new ← P(C₁ $\oplus $ C₃)
12 R_1new' ← nonce $\oplus $ R_1new
13 R_2new ← P(C₂ $\oplus $ C₃)
14 R_2new' ← nonce $\oplus $ R_2new
15 R_3new ← P(C₃ $\oplus $ nonce)
16 R_3new' ← R_3new $\oplus $ nonce
17 H_client ← H(R_1new ∥ R_2new ∥ R_3new ∥ R₁″)
18 return R_1new'，R_2new'，R_3new'，R₁'，H_client

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表 1 安全认证协议指令编码信息表

指令二进制编码	功能描述
算法2 安全WiFi认证算法(4.2节)
32’b0000_000010_000011_000000_00001_0_01_1_1	计算 R3 = P(C3)
32’b0000_000011_000010_000000_00010_1_01_1_1	计算 nonce = R3 $\oplus $ R3'
32’b0000_000100_000011_000000_00010_1_01_1_1	计算 C2 = C2' $\oplus $ nonce
32’b0000_000101_000011_000000_00010_1_01_1_1	计算 R2 = R2' $\oplus $ nonce
32’b0000_000110_000011_000100_00001_0_01_1_1	计算 P(C2)
32’b0000_111111_000101_000110_00101_1_01_1_1	验证 R2 与 P(C2) 是否相等
…	…
32’b0000_010010_001001_001011_00000_0_01_1_0	计算 Hclient = H(R1new \|\| R2new \|\| R3new \|\| R1'')
算法3 软硬件认证协议(4.3节)
32’b0000_111111_000010_000001_00101_1_01_1_1	验证 ID
32’b0000_000101_000100_000011_00010_1_01_1_1	计算 A′ = A $\oplus $ R
32’b0000_000100_000000_000000_00001_0_01_1_1	计算 R = P(C)
32’b0000_000110_000100_000101_00010_1_01_1_1	计算 A = A′ $\oplus $ R

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3 基于PUF的软硬件绑定认证协议

输入：设备标识 ID(C)，应用标识 ID(A)，原始应用A，服务器　端预存CRP数据库
输出：仅在合法设备C上正确执行的应用运行结果
客户端(设备C)：
1 用户获取内嵌PUF的设备C
2 向服务器发起应用A的下载请求
3 发送 {ID(C)，ID(A)} 至服务器
服务器：
4 验证 ID(C) 与 ID(A) 的合法性
5 R ← CRP_database[ID(C)]
6 A′ ← Obfuscate(A，R)
7 将受保护应用A′下发至客户端
客户端(设备C)：
8 R* ← 片上PUF实时生成的响应
9 以R*解混淆并运行A′
10 return 与设备绑定的执行结果

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表 2 三类实现方式的访问延迟对比

实现方式	访问延迟
OA	8944 ns
FSM	6062 ns
IBSCA	6802 ns

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