嵌入式FPGA架构参数化描述框架及多目标QoR架构探索

周婧; 张盛兵; 陈雷; 冯涵旭; 王硕; 田春生

doi:10.11999/JEIT260609

嵌入式FPGA架构参数化描述框架及多目标QoR架构探索

doi: 10.11999/JEIT260609 cstr: 32379.14.JEIT260609

周婧^{1, 2},
张盛兵¹,
陈雷²,
冯涵旭²,
王硕²,
田春生²

1.
西北工业大学，西安市友谊西路127号 710072
2.
北京微电子技术研究所，北京市丰台区四营门北路2号 100070

详细信息

作者简介:
周婧：女，高工，研究方向为FPGA以及嵌入式FPGA架构设计、FPGA EDA软件设计

张盛兵：男，教授，研究方向为高性能计算体系结构、领域专用计算体系结构、集成电路设计

陈雷：男，研究员，研究方向为人工智能算法、集成电路设计

冯涵旭：男，工程师，研究方向为辐射效应、高可靠FPGA设计及应用

王硕：男，研究员，研究方向为FPGA EDA软件设计、FPGA EDA算法

田春生：男，高工，研究方向为FPGA EDA算法、高效布局布线算法

中图分类号: TN47
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出版历程
- 修回日期: 2026-07-29
- 录用日期: 2026-07-29
- 网络出版日期: 2026-08-08

A Parametric Architecture Description Framework for Embedded FPGAs and Multi-objective QoR-driven Architecture Exploration

1.
Northwestern Polytechnical University, Xi’an 710072, China
2.
Beijing Microelectronics Technology Institution, Beijing 100070, China

摘要

摘要: 相较于传统的货架FPGA，嵌入式FPGA的最大区别在于允许开发者根据特定应用的需求独立选择最合适的硬件架构参数(K、N、互连拓扑等)，这就使得架构空间探索不再仅仅是纯学术领域的研究方法，也是必须评估数十上百份架构文件并反复迭代选型的实际工程任务。现有的架构描述框架仍以手工编写架构文件与批处理脚本为主，每次参数调整都要在多份后端文件间逐处同步，难以支撑规模化的架构探索。针对此问题本文提出一种支持多后端架构文件统一描述的参数化架构描述框架，该框架将架构参数按独立性分为工艺常量、耦合参数与独立参数三层，各后端描述由独立的渲染函数自动派生。目前该框架已适配VPR、OpenFPGA、Yosys三路后端并成功扩展至COFFE，并已通过跨工具链全流程验证。依托该框架批量生成架构描述文件，提出基于参数扫描的架构探索方法，系统扫描了查找表(LUT)输入数K与簇规模N的取值组合，从面积、关键路径延迟及二者乘积三个维度衡量每种参数配置的质量结果。结果显示，面积与延迟在(K,N)参数的优化偏好上呈相反方向。还公开发布了一份涵盖5个应用域、包含同构与异构架构的Quality of Results (QoR)数据集，可作为eFPGA架构空间探索的公共标准测试集。
- 嵌入式FPGA /
- 架构空间探索 /
- 参数化架构描述框架 /
- QoR数据集
Abstract: Objective Architecture parameters of Commercial off-the-shelf Field Programmable Gate Arrays (FPGAs) are fixed by the vendor and reused across products. Embedded FPGAs (eFPGAs) leave that choice to the architect, so the LUT input size K, the cluster size N, the interconnect topology, and the heterogeneous tiles are all configurable for the target application. This makes architecture exploration a task in design flow, where tens to hundreds of architectures may have to be drafted and compared before one is settled on. The way architectures are described today holds such exploration back: every architecture is written out by hand and re-aligned across the architecture files of multiple backend toolchains after each parameter change, no formal model keeps these files consistent, and measured QoR data spanning real application domains and heterogeneous tile combinations are rarely shared. To loosen these frictions, the work reported here treats eFPGA architecture description as a research object. The description is given a typed form on which multi-view generation and field-level checking are formally defined, and this model is realized as an open framework that drives the mainstream backend toolchains from one source description. A parameter-sweep design space exploration is then carried out on the framework, and a multi-domain QoR dataset is released alongside as a public benchmark. Methods HorizonArch, the parametric framework proposed in this work, organizes architecture parameters into three independence layers (Table 1). L0 captures process invariants that depend only on the technology node; L1 holds coupled parameters such as K, N, segment length, switch block type, and channel connectivity, where one change forces updates across many fields in the architecture files of different backend toolchains; and L2 holds independent parameters that the architect can set on their own. Architecture construction is formalized as one operator B that maps a parameter vector p to a complete architecture object (Fig. 4), governed by five formal rules: parameter completeness (R1), fragment independence (R2), type compatibility (R3), explicit coupling (R4), and static checkability (R5). Each backend artifact is then produced by an independent derivation function that consumes the same source object, so adding a new tool requires only one new view rather than edits across all existing ones. Field-level validation runs at load time, and cross-field references are checked before any backend is invoked. The class structure (Fig. 3) splits the architecture into synthesis, circuit, and layout views, with each semantic element declared only once. Three extension levels keep the framework open: G1 adds a black-box module, G2 enlarges the value set of an existing coupled parameter, and G3 introduces a new coupled parameter together with its constrained value set. Built on this framework, a parameter-sweep design space exploration method scans the (K, N) grid and the heterogeneous tile combinations, and assesses each configuration using three QoR metrics: area, critical-path delay (CPD), and area-delay product (ADP), where ADP is a derived composite metric calculated from area and CPD. Results and Discussions End-to-end validation confirms that one source description drives VPR, OpenFPGA, and Yosys consistently; COFFE is validated through interface integration and SPICE startup (Table 4, Table 5), and the G1, G2, and G3 extension experiments all pass the cross-field checks. The design space exploration study then reveals a clear divergence among the three QoR metrics on the (K, N) plane (Fig. 5, Fig. 6). Area is dominated by K and favors small K, and most circuits place their area optimum at K=4 N=4. CPD, in contrast, is mildly negatively correlated with both K and N, and its optimum clusters near (8, 10) and (7, 10). The relative range across the twenty (K, N) points (Table 7) is much larger for area and ADP than for CPD, so parameter choice gives a much bigger lever on cost than on raw delay. A study of default configurations (Table 8) shows that K=4 N=4 reaches the per-circuit ADP optimum on 68% of circuits and stays within about six percent on average, while its CPD deviates by close to fifty percent; K=8 N=10 takes the opposite role, with its CPD deviation cut to 5.9% and 30.8% of circuits hit exactly, but its area and ADP deviations soar past 670% and 480%. A random-forest cross-domain surrogate reaches about 65% top-5 accuracy, so a parameter sweep is still needed when the design target is tight. Conclusions This work presents HorizonArch, a formal multi-backend parametric architecture description framework for eFPGA exploration. The framework drives VPR, OpenFPGA, and Yosys from one source description and exposes an extensible COFFE interface. The parameter-sweep exploration carried out on the framework shows that area and CPD favor opposite directions in the (K, N) plane, which means eFPGA architecture parameters should be chosen against an explicit design target rather than a default value. An open QoR dataset covering five application domains is released alongside as a public benchmark. Future work will complete the COFFE SPICE rewriting component, refit the routing-area coefficient with measured data, and explore more efficient exploration strategies on top of the framework.
- Embedded FPGA (eFPGA) /
- Architecture Design Space Exploration (DSE) /
- Parametric architecture description framework /
- Quality of Results (QoR) dataset

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图 1 HorizonArch框架在FPGA架构描述工具谱中的定位

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图 2 L1耦合参数联动传播路径

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图 3 主要类结构及组合关系

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图 4 构造算子 B 的构造律

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图 5 按应用域和设计规模的每个最优(K,N)取值电路汇总

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图 6 三个指标在 (K, N) 网格上的强度热图

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表 1 字段层次化模型

层级	判定标准	典型例子	修改入口
L0工艺不变量	工艺节点决定即固定	r_minw、CLB/DSP绝对面积系数、金属层R/C	工艺预设
L1耦合参数	单一参数变动引发跨字段联动	$ K $、$ N $、tier、segment段长、$ {F}_{s} $、switch_block类型、$ {F}_{c} $	构造算子B
L2独立参数	可独立取值	features 列表项、架构名	架构实例直接声明

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表 2 架构描述框架的参数扩展能力

粒度	改动面	修改示例
G1YAML加条目	追加BlackboxModel与params.*_modes模式条目	双端口BRAM异构模块
G2现有参数加取值	数值参数追加取值，必要时扩展模板分支	BRAM容量、DSP位宽
G3加受约束枚举	新增枚举白名单及对应模板分支	进位链三种实现形式

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表 3 三类架构编写方法的能力对比

维度	手工	简单替换脚本	本框架
跨后端字段一致	人工对齐	在脚本内手写对齐逻辑	单源声明，变换同步
跨字段约束R1–R5	人工保证	不检查	加载期校验
新片段类型支持	重写架构	改脚本本身	G1–G3的扩展层级

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表 4 本文框架与已有开源架构工具的技术差异

维度	HorizonArch框架	OpenFPGA^[1]	iFAR^[16]	FABulous^[2]	PRGA^[3]
主要产出	HorizonArch+QoR数据集	可综合fabric	架构库+面积时序估计	tile级fabric	可组合fabric
工具链支持	3路核心工具链+COFFE扩展	2路	1路	1路	1路
架构描述格式	YAML+pydantic schema	扩展XML	XML手工编辑	CSV+模板	Python DSL
架构生成机制	构造算子B +规则校验	XML模板继承	手工模板替换	tile 级模板组装	Python类继承
扩展方式	G1-G3三档扩展	沿用XML模板继承	XML手工修改	改模板	改Python类

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表 5 基于HorizonArch框架的eFPGA DSE方法

项	取值
应用域	crypto, comm, ctrl, dsp, ml
基准电路	64
K	4, 5, 6, 7, 8
N	4, 6, 8, 10
异构tile组合	LUT only, DSP, BRAM, DSP and BRAM both
每案例扫描配置	5 × 4 = 20 个 (K, N)对
案例总数	156
VPR 配置	VTR 8.0, $ L=4 $, $ \text{fc}\_\text{in=}0.15 $

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表 6 三种QoR的 rel_range 分布

指标	均值	中位数	P90	rel_range>100%占比
CPD	50.9%	48.5%	75.7%	3.8%
area	675.1%	740.1%	935.6%	98.1%
ADP	516.3%	509.4%	742.0%	97.4%

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表 7 默认配置策略的多指标对比

默认配置	CPD 平均偏离	area 平均偏离	ADP 平均偏离	对应 metric 命中率
随机选取	19.7%	234.4%	174.8%	—
K=4 N=4	47.9%	0.6%	5.8%	ADP 67.9%
K=8 N=10	5.9%	673.2%	487.0%	CPD 30.8%

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