V-Agent：RISC-V自定义算术IP集成的协议驱动多智能体框架

李拓; 王长红; 程超; 李国庆; 李南君

doi:10.11999/JEIT260073

V-Agent：RISC-V自定义算术IP集成的协议驱动多智能体框架

doi: 10.11999/JEIT260073 cstr: 32379.14.JEIT260073

李拓^1,,
王长红^2, ,,
程超²,
李国庆¹,
李南君¹

1.
山东云海国创云计算装备产业创新中心有限公司济南 250000
2.
济南迈威智能科技有限公司济南 250000

详细信息

作者简介:
李拓：男，硕士，研究方向为芯片设计与系统架构。　lituo@inspur.com

王长红：男，博士，研究方向为计算机体系结构与数字信号处理。　wangchh01@inspur.com

程超：男，博士，研究方向为密码算法硬件加速、安全协处理器与AI芯片

李国庆：男，博士，研究方向为人工智能加速器与边缘AI芯片

李南君：男，博士，研究方向为人工智能算法设计与可重构硬件实现

通讯作者:
王长红　wangchh01@inspur.com

中图分类号: TN79
计量
- 文章访问数: 8
- HTML全文浏览量: 1
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- 被引次数: 0
出版历程
- 修回日期: 2026-09-17
- 录用日期: 2026-09-17
- 网络出版日期: 2026-09-24

V-Agent: A Protocol-Driven Multi-Agent Framework for RISC-V Custom Arithmetic IP Integration

1.
Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co., Ltd., Jinan 250000, China
2.
Jinan Maxwell Smart Technology Co., Ltd., Jinan 250000, China

摘要

摘要: 针对大语言模型生成多模块寄存器传输级(Register Transfer Level, RTL)代码时，端口名称、方向和位宽不一致易导致集成失败的问题，提出V-Agent协议驱动多智能体框架。框架由架构、控制单元、数据通路和验证4类智能体组成，以JSON接口契约显式描述模块边界，并通过Verilog抽象语法树(Abstract Syntax Tree, AST)比对、编译/仿真诊断和受限重试形成“生成—检查—反馈—修复”闭环。在RISC-V单周期内核集成32位有符号组合乘法器IP的任务上，对6种大语言模型后端进行评测。纯自动化模式下，DeepSeek-V3和Claude-4.5生成的设计均实现8/8个模块编译通过并通过70/78条自动测试；人工在环修复后，6个设计均通过统一的78条测试，平均行级代码变动率为4.37%。结果表明，接口契约能够将跨智能体的隐式接口假设转化为可检查对象，并利用工具诊断定位局部生成错误，为RISC-V自定义算术IP的部分自动化集成提供了可执行的工作流。
- 多智能体系统 /
- 大语言模型 /
- RISC-V /
- 算术IP集成
Abstract: Objective Large language models (LLMs) can assist register-transfer-level (RTL) generation, but processor-level designs require coordination among independently generated control, datapath, top-level, and verification modules. Inconsistent port names, directions, widths, or signal types can block compilation and make repair dependent on manual diagnosis. V-Agent is proposed as a protocol-driven multi-agent framework that converts such interface assumptions into explicit, machine-checkable contracts and routes tool diagnostics back to the responsible generator. Four specialized agents handle architecture specification, control logic, datapath integration, and verification. A single-cycle RISC-V processor integrating a predefined 32-bit signed combinational multiplier IP is used as a controlled task to evaluate multi-module generation, localized error correction, and differences among LLM backends. The workflow therefore targets the integration gap between isolated code generation and executable processor-level verification, with emphasis on whether structural assumptions can be exposed early enough to support bounded, module-local regeneration. Methods V-Agent receives a hierarchical JavaScript Object Notation (JSON) configuration containing the selected LLM backend, generation and retry parameters, architecture attributes, task operations, data widths, and test cases. The Architect Agent generates top-level ports, control signals, datapath components, and operation-code mappings; the Control Unit Agent produces synthesizable decoding and control logic; the Datapath Agent generates arithmetic, register-file, program-counter, routing, and top-level integration logic and instantiates the fixed multiplier IP; and the Verification Agent produces memory models, testbenches, Verilator drivers, and execution scripts. The processor and accelerator organization is shown in Fig. 1, and the multi-agent and verification feedback loops are summarized in Figs. 2 and 3. Port names, directions, widths, and types are recorded in JSON interface contracts. A static analyzer parses the Verilog abstract syntax tree (AST) and compares generated port signatures with the contracts. Compilation and simulation add syntax, connection, and functional diagnostics. Failed checks are returned to the responsible agent and trigger regeneration, with max_retries set to 3. A fallback template is used only when repeated generation reaches the retry limit, allowing the remaining integration and verification steps to continue. The task implements two standard instructions and three experimental custom operations, MLOAD, PMUL, and PMAC. Six LLM backends—DeepSeek-V3, Claude Sonnet 4.5, Doubao-1.5 Pro, Gemini 1.5 Flash, Qwen3-235B, and GPT-5.1—are evaluated using module compilation, automatic tests, Code Quality Score, line-level repair changes, and backend power-performance-area (PPA) outputs. Fully automated results are recorded before manual modification, whereas human-in-the-loop (HITL) results are measured after localized repair. Results and Discussions The monolithic one-shot baseline outputs fail system-level compilation because of context, interface, connection, or incomplete-state-logic problems, whereas the V-Agent pipeline produces samples that can enter system-level compilation (Table 4). This observation is limited to the present benchmark. In fully automated evaluation, DeepSeek-V3 and Claude-4.5 complete all five task operations, compile all eight RTL modules, and pass 70 of 78 automatic tests (Table 6). Doubao-Pro and Gemini-Flash compile 6 of 8 modules, GPT-5.1 compiles 7 of 8, and Qwen3-235B compiles 4 of 8. Because executable automatic-test workloads differ among generated outputs, raw counts and denominators are retained rather than treated as a uniform benchmark; completion and test-pass ratios are shown in Fig. 4. A width-mismatch case demonstrates the feedback mechanism: the Datapath Agent initially generates a one-bit MemToReg signal, while the additional multiplier result path requires a two-bit selector. Contract checking identifies the mismatch, returns the diagnostic to the responsible agent, and completes regeneration in approximately 15 s before compilation and testing pass (Table 7). In the complete case study, the four agents generate eight RTL modules and 17 verification files in about 5 min; all eight modules compile, and four system-level programs produce the expected final register states and waveforms. The generated arithmetic execution and writeback path is shown in Fig. 5. After localized HITL edits, all six designs compile 8 of 8 modules and pass the same 78 tests. The average line-level code-change rate is 4.37%, ranging from 1.3% to 9.5% (Table 9). Backend analysis shows that Claude, DeepSeek, and Gemini complete synthesis and timing analysis, while GPT-5.1 does not converge because of a combinational loop and the unusually small Doubao and Qwen implementations exhibit synthesis pruning (Table 8). Among 126 classified generation- and compilation-stage errors, 54 are Verilog semantic errors, 36 are interface-width errors, 26 are cascading failures, and 10 are custom-operation semantic errors (Table 10). Conclusions V-Agent organizes processor RTL generation as cooperation among specialized agents connected by explicit interface contracts and tool feedback. The evaluated RISC-V arithmetic-IP task shows that structural interface mismatches can be localized and corrected without regenerating the complete design, while HITL results separate initial generation quality from engineering repairability. The principal contribution is a coordination mechanism that turns cross-module assumptions into checkable contracts and returns AST, compilation, and simulation diagnostics to the responsible generator, rather than a replacement for established synthesis, simulation, high-level synthesis, or verification tools. The evidence is limited to a single-cycle RISC-V core, a fixed 32-bit multiplier IP, 5–15 task operations, and nonuniform executable test workloads. Verilator cannot expose every timing defect, and the PPA study requires more complete activity, supply, and netlist conditions. Future work will extend the workflow to pipelined processors and coverage-guided automated repair.
- Multi-Agent Systems /
- Large language models /
- RISC-V /
- Arithmetic IP Integration

HTML全文

图 1 RISC-V核与CIM算术加速路径的逻辑集成架构

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图 2 V-Agent协议驱动多智能体架构及自动化/HITL反馈流程

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图 3 V-Agent的生成、静态检查、Verilator仿真与错误反馈闭环

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图 4 六个LLM后端及人工基准的FCR与自动测试通过率

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图 5 CIM算术执行单元原型的操作数选择、乘法执行与结果回写路径

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表 1 基于LLM的硬件设计方法比较

方法	M-A	Verif.	S-C	Custom Op.
RTLCoder	$ \times $	$ \times $	$ \times $	$ \times $
ChipGPT	$ \times $	Manual	$ \times $	$ \times $
VeriOpt	$ \mathrm{\checkmark } $	PPA	$ \mathrm{\checkmark } $	$ \times $
REvolution	$ \times $	Evol.	$ \times $	$ \times $
ChipSeek-R1	$ \times $	RL	$ \mathrm{\checkmark } $	$ \times $
V-Agent	$ \mathrm{\checkmark } $	Contract	$ \mathrm{\checkmark } $	$ \mathrm{\checkmark } $
M-A: Multi-Agent; S-C: Self-Correction; Custom Op.: Experimental Custom Operation

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表 2 实验原型中的自定义算术操作及集成行为

名称	操作码	操作数来源	集成行为
MLOAD	0001011	数据存储器	读取数据并写回寄存器
PMUL	0101011	两个寄存器操作数	调用32位有符号乘法器并写回
PMAC	0011011	存储器数据与寄存器数据	调用乘法器并接入回写路径

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表 3 RISC-V自定义算术IP集成任务配置与复杂度指标

属性	数值	说明
设计配置
体系结构	单周期	RISC-V单周期数据通路
任务操作项总数	5	2条标准指令 + 3个实验性自定义操作
标准指令	2	ADDI, ADD
实验性自定义操作	3	MLOAD、PMUL、PMAC
设计复杂度
RTL模块数	8	可综合模块
接口信号数	43	模块间信号总数
代码行数	$ \sim $370	生成的Verilog代码
圈复杂度	2.11–2.89	控制流复杂度
测试用例数	78	功能验证测试

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表 6 RISC-V自定义算术IP集成任务(5个任务操作项)的跨模型原始计数

模型	通过的操作项	语法错误	模块编译	自动测试	人工修复后测试	CQS
DeepSeek-V3	5/5	0	8/8	70/78	78/78	65.7
Claude-4.5	5/5	0	8/8	70/78	78/78	65.9
Doubao-Pro	5/5	28	6/8	64/78	78/78	65.7
Gemini-Flash	4/5	32	6/8	70/81	78/78	71.7
Qwen3-235B	5/5	34	4/8	40/50	78/78	64.0
GPT-5.1	4/5	10	7/8	70/81	78/78	68.9
注：“通过的操作项”按5个任务操作项统计；自动测试按各模型生成后可执行的测试样本统计，因此分母随生成结果变化；人工修复后统一使用78条测试。

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表 4 单体式基线与V-Agent的首轮编译记录

模型配置 (Model)	生成代码输出量 (字符数)	结构与接口状态	首轮编译结果
V-Agent Pipeline(最佳后端)	按需动态分配多轮生成	完成接口检查与系统级集成	获得可编译系统样本
claude-sonnet-4-5-20250929	～21,993字符	未通过(上下文与连线不一致)	未通过
gemini-1.5-flash	～16,757字符	未通过(语法错误或端口未定义)	未通过
deepseek-chat	～7,925字符	未通过(模块划分与接口不一致)	未通过
gpt-5.1	～6,949字符	未通过(数据通路连线缺失)	未通过
doubao-1.5-pro	～4,849字符	未通过(单次输出未完成状态逻辑)	未通过

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表 7 各智能体在接口检查与反馈重试中的职责和案例记录

智能体	检查与反馈职责	案例中的反馈记录	处理结果
架构智能体	生成模块接口契约	完成接口字段定义	契约用于后续模块生成
控制单元智能体	处理操作码译码与控制信号	1次反馈重试	完成译码逻辑修正
数据通路智能体	处理端口、数据通路与顶层连线	2次反馈重试	完成端口与连线修正
验证智能体	汇总AST、编译与测试诊断	诊断信息回传对应智能体	驱动编译与测试闭环

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表 8 各模型生成代码经人工修复后的PPA结果(Nangate45, 45 nm, 500 MHz)

模型	面积(μm²)	延迟(ns)	功耗(mW)	DFF	状态
Claude	9,739.32	0.468	0.00298	1022	流程完成*
DeepSeek	10371.34	1.174	0.00597	1022	流程完成*
Gemini	10640.53	0.963	0.00631	1022	流程完成*
GPT-5.1	9918.61	N/A	N/A	1022	STA未收敛*
Doubao	327.45	0.374	0.00007	30	综合裁剪†
Qwen	897.48	0.655	0.00027	61	综合裁剪†
注：* Claude、DeepSeek和Gemini完成综合与时序分析；GPT-5.1完成门级映射，但组合环路导致STA未收敛。† Doubao和Qwen的DFF数量与面积异常偏低，综合日志显示存在大规模逻辑裁剪，因此两项结果用于分析代码结构与综合优化的交互。

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表 5 V-Agent在不同任务操作项规模下的编译结果

任务操作项规模	要求支持的任务操作项	编译结果	任务特征
LOW (轻量)	ADD、SUB(2项)	获得可编译样本	基础算术
MEDIUM (标准)	ADD、SUB、AND、OR、XOR(5项)	获得可编译样本	多操作ALU
CUSTOM_IP	MLOAD、PMUL、PMAC(实验性操作)	获得可编译样本	算术IP集成
HIGH (复杂)	含SLT、BEQ、BNE等10项以上	获得可编译样本	分支与控制流

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表 9 人工修复实验的行级代码变动统计

模型	原始行数	修复后行数	代码变动行数(增/删/改)	行级代码变动率
Claude-4.5	537	544	7	1.3%
Qwen3-235B	422	440	40	9.5%
DeepSeek-V3	488	488	40	8.2%
Doubao-Pro	465	473	12	2.6%
GPT-5.1	551	558	11	2.0%
Gemini-1.5	665	674	17	2.6%
注：变动行数为新增、删除和修改行数之和；行级代码变动率=变动行数/原始行数×100%，不等于修复后行数与原始行数之差。

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表 10 生成与编译阶段的失败类型统计(N=126)

模型	语义错误	位宽错误	级联失败	自定义操作语义
DeepSeek	未归类	未归类	未归类	未归类
Claude	未归类	未归类	未归类	未归类
Gemini	10	6	4	2
Doubao	12	8	6	2
GPT-5.1	18	12	8	4
Qwen	14	10	8	2

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