Space-based Computing Chips: Current Status, Trends and Key Technique

WEI Xiaotong; XU Haobo; YIN Chundi; HUANG Junpei; SUN Wenhao; XU Wenjun; WANG Ying; LIU Yaoqi; MENG Fantao; MIN Feng; WANG Mengdi; HAN Yinhe

doi:10.11999/JEIT250633

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WEI Xiaotong, XU Haobo, YIN Chundi, HUANG Junpei, SUN Wenhao, XU Wenjun, WANG Ying, LIU Yaoqi, MENG Fantao, MIN Feng, WANG Mengdi, HAN Yinhe. Space-based Computing Chips: Current Status, Trends and Key Technique[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250633

Citation:

WEI Xiaotong, XU Haobo, YIN Chundi, HUANG Junpei, SUN Wenhao, XU Wenjun, WANG Ying, LIU Yaoqi, MENG Fantao, MIN Feng, WANG Mengdi, HAN Yinhe. Space-based Computing Chips: Current Status, Trends and Key Technique[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250633

Citation:

WEI Xiaotong, XU Haobo, YIN Chundi, HUANG Junpei, SUN Wenhao, XU Wenjun, WANG Ying, LIU Yaoqi, MENG Fantao, MIN Feng, WANG Mengdi, HAN Yinhe. Space-based Computing Chips: Current Status, Trends and Key Technique[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250633

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Space-based Computing Chips: Current Status, Trends and Key Technique

doi: 10.11999/JEIT250633 cstr: 32379.14.JEIT250633

WEI Xiaotong^{1, 2, 3, 4},
XU Haobo^{1, 2},
YIN Chundi^{1, 2},
HUANG Junpei^{1, 2},
SUN Wenhao^{1, 2},
XU Wenjun^{1, 2},
WANG Ying^{1, 2},
LIU Yaoqi^{1, 2},
MENG Fantao^{1, 2},
MIN Feng^{1, 2},
WANG Mengdi^{1, 2},
HAN Yinhe^{1, 2
,
,}

1.
SKLP, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
2.
Research Center for Intelligent Computing Systems, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
3.
Hangzhou Institute for Advanced Study, Hangzhou 310024, China
4.
University of Chinese Academy of Sciences, Beijing 101408, China

Funds: The National Natural Science Foundation of China (62025404, 62495104), Beijing Natural Science Foundation (L241013)

Received Date: 2025-07-04
Rev Recd Date: 2025-09-05

Available Online: 2025-09-17

Abstract

Abstract

Significance With the continuous advancement of aerospace technology and the growing demand for space applications, space-based computing chips have assumed increasingly important strategic roles as core hardware infrastructure of space information systems. As the technological foundation enabling intelligent data processing and reliable communications for spacecraft—including satellite platforms, space stations, and deep space probes—space-based computing chips not only safeguard national security and support economic development but also play an irreplaceable role in serving civilian needs. Although existing survey literature has systematically reviewed the development of aerospace Central Processing Units (CPUs), comprehensive analyses of other key components within the space-based computing chip ecosystem remain limited. To address this gap, this paper systematically examines the technological evolution of various space-based computing chips and their principal fault-tolerant mechanisms, and further explores potential future trends in this field. Progress This paper adopts a functional architecture-oriented classification to systematically analyze and summarize the current technological status of space-based computing chips across three dimensions: CPU, Field-Programmable Gate Array (FPGA), and dedicated chip. For CPU technology, a classification study of general-purpose processors widely used in aerospace applications is conducted based on instruction set architectures, with in-depth analysis of the technical characteristics and representative products of various architectures, together with an objective evaluation of their advantages and limitations in space environments. In the FPGA domain, the technical specifications and performance characteristics of mainstream space-grade FPGA products, both domestic and international, are comprehensively reviewed to provide a reference for application selection. For dedicated chips, a detailed categorization is carried out according to functional architectural features and application scenario requirements, covering Digital Signal Processing (DSP) chips for signal processing acceleration, Graphics Processing Unit (GPU) chips for graphics computation, and Neural Processing Unit (NPU) chips for space-based artificial intelligence applications, thereby systematically clarifying the applicability of different architectures in complex space environments. In addition, this paper presents an in-depth analysis of the key fault-tolerant technology framework for space-based computing chips at multiple levels, including system, architecture, circuit, and process library, and provides a comprehensive evaluation of the technical advantages, application limitations, and development prospects of various fault-tolerant mechanisms. This analysis offers theoretical guidance for the reliability design of space-based computing chips. Conclusions This review systematically summarizes the technological development of space-based computing chips, providing a comprehensive analysis of the architectural characteristics of different chip types and their associated fault-tolerant technology frameworks, while elucidating the applicable scenarios and technical limitations of various fault-tolerant mechanisms. The central principle of fault-tolerant design for space-based computing chips is to achieve effective detection and correction of circuit faults through redundancy mechanisms. This paper offers an in-depth analysis of the implementation principles and application characteristics of fault-tolerant technologies at four hierarchical levels: system, architecture, circuit, and process library. Although these multi-level approaches substantially improve system reliability, they inevitably introduce hardware resource overhead and performance penalties. Therefore, the engineering design of space-based computing chips requires optimized strategies that combine multi-level fault-tolerant technologies according to specific reliability requirements, aiming to balance reliability, cost, and performance to meet the intended design objectives and technical specifications. Prospects Looking ahead, space-based computing chips present broad prospects in high computing capability, widespread adoption of Commercial Off-The-Shelf (COTS) devices, and the development of Reduced Instruction Set Computer – Five (RISC-V) instruction set architectures. With the rapid advancement of space technology, space-based systems are undergoing a transformation from traditional single-function platforms to integrated platforms characterized by multi-task collaboration, autonomy, and intelligence. Real-time data processing, multi-task parallel computing, and intelligent decision-making have become the principal driving forces in the evolution of space-based computing technology, all of which demand robust computational foundations. Compared with traditional radiation-hardened specialized devices, COTS devices are emerging as a major trend in space-based computing chip development due to their advantages in cost-effectiveness, computational performance, shorter development cycles, and product diversity. In addition, RISC-V, as an open-source instruction set architecture, offers unique advantages and significant potential for space-based computing chip innovation through its modular design philosophy, exceptional scalability, and open ecosystem.
- Space-based computing chips,
- Fault-tolerant technology,
- High computing capability,
- Commercial Off-The-Shelf (COTS),
- RISC-V

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