A Survey of Data Prefetcher Security on Modern Processors

LIU Chang; HUANG Qilin; LIU Yuchuan; LIN Shihong; QIN Zhongyuan; CHEN Liquan; LYU Yongqiang

doi:10.11999/JEIT250412

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LIU Chang, HUANG Qilin, LIU Yuchuan, LIN Shihong, QIN Zhongyuan, CHEN Liquan, LYU Yongqiang. A Survey of Data Prefetcher Security on Modern Processors[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250412

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LIU Chang, HUANG Qilin, LIU Yuchuan, LIN Shihong, QIN Zhongyuan, CHEN Liquan, LYU Yongqiang. A Survey of Data Prefetcher Security on Modern Processors[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250412

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A Survey of Data Prefetcher Security on Modern Processors

doi: 10.11999/JEIT250412 cstr: 32379.14.JEIT250412

1.
Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China
2.
School Of Cyber Science and Engineering, Southeast University, Nanjing 211189, China
3.
Beijing National Research Center for Information Science and Technology, Tsinghua University, Beijing 100084, China

Received Date: 2025-05-13
Rev Recd Date: 2025-08-28

Available Online: 2025-09-02

Abstract

Abstract

Significance The data prefetcher is a key microarchitectural component in modern processors, designed to enhance memory access performance by speculatively preloading data into the cache based on predictions of future access patterns. While effective at reducing cache misses, prefetcher design has historically neglected security considerations, resulting in various forms of information leakage. Recent studies have shown that data prefetchers can be exploited in side-channel attacks targeting cryptographic libraries, operating systems, hypervisors, and trusted execution environments. However, most existing attacks focus on specific implementations (eg., "one-spot" attacks) fail to comprehensively capture the broader attack surface exposed by diverse prefetcher designs. Two fundamental research questions remain open: (1) Do current attacks fully characterize all exploitable vectors in modern prefetchers, or are additional vectors yet to be explored? (2) How can the security of different prefetcher designs be systematically and quantitatively assessed to support comparative analysis and guide secure design? This paper addresses both questions through a systematic survey of data prefetcher attacks and a model-driven analysis. By generalizing known attack mechanisms, this work proposes a formalized framework for understanding and evaluating the security of data prefetchers. Methods To capture the behavior of data prefetchers, this study first presents a memory access model that specifies the instruction address, data address, and access attributes for each memory operation, which can be extended to represent access sequences. Building on this, a prefetcher model is proposed in which a prefetcher is trained by a sequence of memory accesses and triggered by a single access to generate a set of prefetches. Each prefetcher is characterized by design parameters. Attacker and victim profiles are then incorporated to construct attack models based on reduced memory access representations, enabling formalization of 20 known prefetcher-based attacks. Finally, a security evaluation framework is proposed, comprising 24 metrics across three dimensions—design parameters, isolation, and attack feasibility. This framework supports quantitative scoring and comparison of prefetcher designs. Results and Prospects In terms of attack modeling, the analysis shows that the 20 known attacks cover only a limited portion of the overall attack space. This study proposes several previously unexplored attack vectors, including those that exploit cache hit effects and speculative execution, attacks that leverage indexing collisions using instruction and data addresses, and additional side channels resulting from prefetcher-induced effects on other microarchitectural components, such as Translation Lookaside Buffer (TLB) state and cache coherence state. In terms of evaluation, this paper examines five commercial processors featuring different prefetchers: Intel’s Stride prefetcher and eXtended Page Table (XPT), AMD’s Stride prefetcher, Arm’s Spatial Memory Streaming (SMS) prefetcher, and Apple’s Data Memory Prefetcher (DMP). The findings reveal that all five prefetchers exhibit varying degrees of vulnerability to side-channel leakage, depending on their design parameters, isolation strategies, and the feasibility of exploitation. The paper further assesses three mitigation strategies and shows that while some measures substantially enhance security, residual risks remain, highlighting the need for improved countermeasures. Discussion Beyond characterizing existing attack vectors and evaluating the security of current prefetcher implementations, this study also outlines emerging directions for secure prefetcher design. Existing work primarily focuses on the Stride prefetcher, with preliminary defenses based on control registers that allow software to constrain the address range eligible for prefetching. This reduces the likelihood that secret-dependent memory accesses affect prefetcher state or trigger the prefetching of sensitive cache lines. Nevertheless, these approaches remain at an early stage, and a comprehensive framework for the systematic design of secure prefetchers has yet to be developed. Conclusions This paper presents a systematic study of data prefetcher security. It proposes a model-driven framework for analyzing potential attack vectors and introduces a quantitative method for evaluating prefetcher security. These contributions lay a theoretical foundation for identifying new attack mechanisms, guiding the development of effective countermeasures, and informing the secure design of data prefetchers in future processor architectures.
- Computer Architecture,
- Processor,
- Data Prefetcher,
- Microarchitectural Security,
- Side Channel Attack

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References(63)

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