处理器芯片安全综述

陈聪聪; 顾致扬; 张吉良

doi:10.11999/JEIT260026

处理器芯片安全综述

doi: 10.11999/JEIT260026 cstr: 32379.14.JEIT260026

南京邮电大学集成电路科学与工程学院南京 210023

基金项目: 国家自然科学基金(U24A20289)

详细信息

作者简介:
陈聪聪：男，博士，讲师，研究方向为处理器微架构安全、体系结构安全等

顾致扬：男，硕士生，研究方向为处理器微架构安全等

张吉良：男，博士，教授，博导，研究方向为集成电路硬件安全等

通讯作者:
张吉良　zhangjiliang@njupt.edu.cn

中图分类号: TN918; TP309
计量
- 文章访问数: 19
- HTML全文浏览量: 6
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- 被引次数: 0
出版历程
- 收稿日期: 2026-01-08
- 修回日期: 2026-03-18
- 录用日期: 2026-03-24
- 网络出版日期: 2026-04-19

A Survey of Processor Chip Security

School of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210023, China

Funds: The National Natural Science Foundation of China (U24A20289)

摘要

摘要: 处理器芯片安全是信息安全的基石。长期以来，各种密码算法、应用程序和操作系统都以处理器作为可信基础。然而，随着摩尔定律的减缓，现代处理器在微架构设计中不断追求高性能和低功耗的目标，而忽视了安全性，导致近期安全漏洞频发。其中，以Meltdown和Spectre为代表的微架构时间信道漏洞备受关注，它们利用微架构状态变化引起的时间差异来突破基础的软硬件隔离，影响数十亿台主流CPU厂商的设备。此外，由于架构与微架构之间的界限变得模糊，催生了一系列新的攻击方式，使得时间信道从“硬件漏洞”发展为系统级安全问题。然而，现有文献主要基于硬件组件进行分类，掩盖了时序泄露的潜在共性，并限制了对软件信道分析的能力。本文对时间信道进行跨层综述，将基于硬件的和基于软件的泄漏统一在一个共同的抽象模型下。具体而言，我们首先分析了时间信道产生的4个基本条件，并根据核心泄露条件中共享可变状态的性质以及时间观测能力产生的机制将现有的软硬件攻击统一在一个分类模型下。基于该分类，我们全面回顾了近十年的攻击方法，系统地分析了它们的攻击步骤，并揭示了它们之间的共性。其次，基于阻断的泄露条件，我们对现有的防御技术进行分类，并指出防御的作用范围与失效原因。最后，总结了当前的自动化检测方法并对新兴平台下的时间信道安全研究与未来发展趋势进行了前瞻性的讨论。
- 处理器安全 /
- 时间信道 /
- 侧信道攻击 /
- 瞬态执行
Abstract: Significance Processor chip security is widely regarded as the foundation of modern information security. Cryptographic algorithms, operating systems, and applications have traditionally relied on processors as trusted computing bases. However, as Moore’s Law slows, modern processors increasingly adopt aggressive microarchitectural optimizations to improve performance and energy efficiency, often without systematic security consideration. As a result, security vulnerabilities have emerged frequently in recent years. Notably, microarchitectural timing channels exemplified by Meltdown and Spectre exploit timing differences induced by microarchitectural state changes to bypass fundamental hardware and software isolation, affecting billions of devices worldwide. Meanwhile, the boundary between architectural and microarchitectural behavior has become increasingly blurred, giving rise to new attack paradigms and transforming timing channels from isolated hardware flaws into cross-layer system security problems. Progress Although substantial progress has been made in the study of timing channels, existing surveys exhibit several limitations. First, the mechanisms underlying timing channels are highly diverse, with an expanding set of exploitable components, making hardware-centric classifications insufficient to capture emerging and unknown attacks while obscuring commonalities across techniques. Second, as classic microarchitectural channels become better understood and partially mitigated, leakage increasingly migrates to higher-level shared resources, including operating system policies and software-managed coordination mechanisms. However, prior work often treats software primarily as an execution context rather than a source of timing leakage. In addition, existing discussions of defenses tend to focus on individual techniques, with limited analysis of their scope of effectiveness and failure modes. Contributions In this survey, timing channels are systematically reviewed from a cross-layer perspective, and hardware- and software-based leakages are unified under a common abstraction. Four necessary conditions for timing channel exploitation are identified, and a unified classification framework is constructed based on the nature of shared mutable state and the mechanisms enabling timing observability. Within this framework, representative attacks from the past decade are comprehensively reviewed, their attack workflows are analyzed, and underlying commonalities are revealed. Furthermore, existing defense mechanisms are classified according to the leakage conditions they aim to disrupt, and their protection scope as well as potential failure modes are discussed. Finally, this paper also analyzes the current automated detection methods. Prospects Looking forward, timing channel research faces emerging challenges. New hardware optimization techniques continue to introduce novel attack surfaces, while resource sharing at the software level may give rise to additional timing leakage. Moreover, emerging platforms—including chiplet-based architectures, cloud computing environments, hardware accelerators, and heterogeneous systems—are likely to expose new forms of timing channels that warrant systematic investigation.
- Processor security /
- timing channels /
- side-channel attacks /
- transient execution

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图 1 经典侧信道攻击步骤

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图 2 瞬态执行攻击步骤

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表 1 跨层时间信道攻击的统一分类体系

泄露条件	攻击类别		硬件信道实例	软件信道实例
共享状态在上下文切换后仍然保留	状态驻留类	微架构的持久状态	TLB^[11]、LLC^[2,12]、BTB^[13]	——^†
共享状态在上下文切换后仍然保留	状态驻留类	架构的持久状态	DRAMA^[14]、LLM^[15]、MetaLeak^[16]	Page^[5]、Write+Sync^[17]、SLUB^[6]
并发使用导致带宽降低/性能下降	资源竞争类	结构性竞争	提交单元^[18]、带宽^[19]、Reload+Reload^[20]、 LeakyHammer^[21]	KernelSnitch^[22]、Sync+Sync^[23]
并发使用导致带宽降低/性能下降	资源竞争类	仲裁型竞争	CPU环互连^[24]、PCIe^[25]、Mesh^[26]	MES-Attacks^[27,28]
状态实现被延迟，快慢路径可区分	延迟转换类	故障/中断触发延迟	SegScope^[29]、Thermalscope^[30]、Keydrown^[31]、WAIT^[32]	写时复制^[33]
状态实现被延迟，快慢路径可区分	延迟转换类	惰性切换延迟	LazyFP^[34]	——^†
基于历史行为的预测或自适应优化	异步反馈类	预取类	GoFetch^[35]、PrefetchX^[36]	BunnyHop^[37]、Prefetchw^[38]
		预测执行类	Spectre-PHT^[3]、Spectre-RSB^[39]、RIDL^[40]、 Fallout^[41]、ARMeD^[42]、循环预测机制^[43]	——^†
		异常/故障类	Meltdown^[4]、Foreshadow^[44]	——^†
^†当前未发现对应的实例

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表 2 时间信道防御技术分类

防御类别		防御范围/目标	典型实例	防御开销
基于隔离	分支预测器隔离	异步反馈类(分支预测攻击)	BRB^[47]	3.5%～5.5%
			XOR-BP^[48]	～2.5%，0.24%(硬件开销)
			HyBP^[49]	0.5%，21.1%(硬件开销)
	缓存隔离	状态驻留类(缓存侧信道)	PhantomCache^[50]	0.5%～1.2%
	缓存隔离	状态驻留类(缓存侧信道)	DAWG^[51]	<2%
	敏感目标隔离	异步反馈类(异常/故障攻击)	Site Isolation^[52]	9%～13%(内存开销)
	敏感目标隔离	异步反馈类(异常/故障攻击)	KAISER^[53]	1～10%
限制可观测的微架构状态变化	限制推测执行	异步反馈类(预测执行攻击)	Retpoline^[54]	5～10%
	限制推测执行	异步反馈类(预测执行攻击)	CSF^[55]	<8%
	添加硬件结构	异步反馈类(预测执行与异常/故障攻击)	InvisiSpec^[56]	22%，3.5%(面积开销)
	添加硬件结构	异步反馈类(预测执行与异常/故障攻击)	TreasureCache^[57]	<0.5%(硬件开销)
	撤销或阻止不安全推测的影响	异步反馈类(预测执行与异常/故障攻击)	CleanupSpec^[58]	5.1%，～1KB(存储开销)
			NDA^[59]	10.7%～125%
			SCSGuardian^[60]	3.82%～5.97%
			PreFence^[61]	1%
干扰隐蔽信道的测量	注入噪声	时间侧信道	Reuse-trap^[62]	—^†
干扰隐蔽信道的测量	注入噪声	时间侧信道	Prefender^[63]	-1.69%
检测后阻止	代码或特征分析	异步反馈类(预测执行攻击)	Spectector^[64]	—^†
			SpecTaint^[65]	～1.5%-2%
			Spoiler-ALERT^[66]	0.24%
^†文中未给出

下载: 导出CSV

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