低开关比FeFET时序控制非易失性触发器设计

杜世民; 杨畅; 王伦耀; 张哲

doi:10.11999/JEIT251059

低开关比FeFET时序控制非易失性触发器设计

doi: 10.11999/JEIT251059 cstr: 32379.14.JEIT251059

杜世民^{1, 2, ,},
杨畅^{1, 2},
王伦耀²,
张哲^{1, 2}

1.
宁波大学科学技术学院宁波 315300
2.
宁波大学信息科学与工程学院宁波 315211

基金项目: 国家自然科学基金项目(U23A20351, 62304115)；浙江省自然科学基金重点项目(LDT23F04021F04)，宁波市智能家电重点实验室开放课题(20250621)

详细信息

作者简介:
杜世民：男，副教授，研究方向为集成电路物理设计优化和存算一体电路设计

杨畅：男，研究生，研究方向为存算一体电路设计

王伦耀：男，教授，研究方向为逻辑综合与优化和存算一体电路设计

张哲：男，研究生，研究方向为集成电路物理设计优化和低功耗设计

通讯作者:
杜世民　dushimin@nbu.edu.cn

中图分类号: TN402
计量
- 文章访问数: 18
- HTML全文浏览量: 6
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- 被引次数: 0
出版历程
- 收稿日期: 2025-10-09
- 修回日期: 2026-05-15
- 录用日期: 2026-05-15
- 网络出版日期: 2026-06-03

Design of a Timing-Controlled Non-Volatile Flip-Flop with Low-Switching-Ratio FeFET

DU Shimin^{1, 2
, ,},
YANG Chang^{1, 2},
WANG Lunyao²,
ZHANG Zhe^{1, 2}

1.
College of Science & Technology Ningbo University, Ningbo 315300, China
2.
Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo 315211, China

Funds: National Natural Science Foundation of China (U23A20351, 62304115), Natural Science Foundation of Zhejiang Province (LDT23F04021F04), Open Project of Ningbo Key Laboratory of Intelligent Home Appliances (20250621)

摘要

摘要: 基于铁电场效应晶体管(FeFET)的非易失性触发器(NVFF)具有高效、快速数据备份与恢复能力，是提升非易失性处理器(NVPs)性能的有效途径。然而，研究表明，FeFET开关比降低时，传统单端结构触发器在断电恢复过程中易受锁存器内部MOS管竞争影响，导致FeFET存储状态改变，造成数据恢复失败。为解决这一问题，该文提出一种面向静态无争用单相时钟触发器(SSCFF)的单端恢复电路。该结构在CLK=0时保持FeFET写入节点维持高电平，从源头避免竞争导致FeFET存储状态改变；同时提出“预充电–状态调控放电”双阶段恢复机制，实现断电前数据精准恢复。实验结果表明，该方案在FeFET开关比降至10²条件下，经过2000次蒙特卡洛仿真仍能保持100 %恢复率，较现有单端结构所需开关比降低两个数量级。此外，该设计在维持飞焦耳(fJ)量级恢复功耗下，最坏保持时间减少64.6 %，时钟至输出延迟降低33.9 %。
- 铁电场效应晶体管 /
- 非易失性触发器 /
- 单端集成结构 /
- 静态无争用单相时钟触发器
Abstract: Objective Nonvolatile processors(NVPs) have become a key technology for Internet-of-Things (IoT) and energy-harvesting systems, where maintaining computational states during unexpected power interruptions is essential. Conventional volatile processors rely on external nonvolatile memory(NVM) for state retention; however, this approach incurs significant latency and energy overheads. Integrated nonvolatile flip-flops using ferroelectric field-effect transistors(FeFETs) offer a promising alternative by enabling on-chip state backup and recovery. Nevertheless, existing single-ended FeFET-based flip-flops are prone to contention-induced failures during power-up recovery, especially when the FeFET on/off ratio degrades. This issue originates from competing discharge paths that lead to uncertainty in internal node voltage settling, thereby resulting in unreliable state restoration. To address this challenge, this work proposes a novel flip-flop architecture that replaces contention-based recovery with a timing-controlled two-phase mechanism. The primary objectives of this design are to achieve high-reliability recovery even under degraded FeFET on/off ratios as low as 10², optimize timing parameters such as Hold-Time and Clock-to-Q delay, and maintain low energy consumption suitable for IoT applications. Methods The proposed design is an extension of the Static Contention-Free Single-Phase-Clocked Flip-Flop(SSCFF), which inherently eliminates internal node contention through its fully static structure. Based on this foundation, one FeFET device and five additional MOSFETs are integrated to construct a single-ended nonvolatile flip-flop(NVFF). Two control signals, RES and MOD, are introduced to manage the recovery process.In the normal operation mode where MOD=0, the circuit functions as a conventional SSCFF and supports state backup during runtime. In the recovery mode where MOD=1, the recovery operation is divided into two distinct phases.In the pre-charge phase, when RES=0, the internal nodes are pre-charged to VDD. In the selective discharge phase, as RES transitions from low to high, the resistance state of the FeFET determines whether discharge occurs. If the FeFET is in the low-resistance state(LRS), a discharge path is formed, pulling the node voltage down to ground. If the FeFET remains in the high-resistance state(HRS), the node retains its charge until the next clock edge.This sequence of pre-charging followed by selective discharge eliminates contention during recovery and ensures that the internal node voltages settle deterministically and reliably.The design is implemented in a 130nm CMOS process with integrated FeFET models. Simulations, including Monte Carlo analysis, were performed in Cadence Virtuoso across a supply voltage range of 0.6–0.9 V and FeFET on/off ratios ranging from 10² to 10⁴. Key performance metrics, such as Setup-Time, Hold-Time, Clock-to-Q delay, restore energy, and recovery success rate, were evaluated and compared against traditional Transmission Gate Flip-Flop. Results and Discussions Simulation results show that the timing-controlled recovery improves reliability even under severe FeFET degradation. The proposed flip-flop achieves 100 % restore yield when the FeFET on/off ratio drops to 10². This is because the proposed structure eliminates the competing discharge paths. Timing metrics are also improved: the 3σ worst-case Hold-Time is reduced by 64.6 % , and the Clock-to-Q delay is shortened by 33.9 %. Although Setup-Time increases slightly, it can be compensated by device sizing. Restore energy remains in the low-fJ (10^–15 J) range across all supply voltages, rising only modestly compared with the TGFF because of the added pre-charge phase. Conclusions A Ferroelectric FET Nonvolatile Flip-Flop with timing-controlled two-phase recovery has been presented, addressing the contention-induced failure modes that limit low-voltage NVFF reliability. By integrating a single FeFET with an enhanced SSCFF structure and using RES signal to manage the pre-charge and discharge steps, high restore yield is maintained even under severely degraded FeFET on/off ratios, while Hold-Time and Clock-to-Q delay are significantly improved relative to traditional transmission-gate NVFFs. The proposed architecture offers a compelling solution for energy-constrained IoT processors requiring fast, reliable state preservation under unpredictable power conditions.
- Ferroelectric Field Effect Transistor /
- Nonvolatile Flip-Flop (NVFF) /
- Single-Ended Structure /
- Static Contention-Free Single-Phase-Clocked Flip Flop

HTML全文

图 1 FeFET的基本结构与极化状态

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图 2 FeFET等效电路与滞回曲线

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图 3 铁电触发器电路图

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图 4 FeFET-SSCFF电路结构与恢复阶段部分电路状态图

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图 5 FeFET-SSCFF工作时序图

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图 6 节点n₁与n₂在恢复阶段的电压变化

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图 7 基于FeFET的铁电触发器在计数器中的应用

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图 8 基于铁电触发器的RISC-V设计

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图 9 正常模式下时序指标随电源电压(VDD)变化趋势

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图 10 功耗变化趋势

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图 11 恢复模式下指标变化趋势

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表 1 FeFET部分模拟参数

属性	属性值
宽度	280 nm
长度	130 nm
阈值电压	0.4 V
温度	298 K
阈值电压影响因子	0.1 V/V
导通电流	80 μA
关闭电流	28 nA
铁电层厚度	10 nm

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表 2 与相关文献的结果比较

特性参数	RRAM- NVFF[28]	FeFET- SAFF[2]	FeFET- TGFF-1[24]	FeFET- TGFF-2[11]	FeFET- TGFF-3[11]	FeFET- TGFF-4[25]	FeFET- TGFF-5[14]	本工作
非易失性材质	RRAM	FeFET	FeFET	FeFET	FeFET	FeFET	FeFET	FeFET
工艺尺寸/nm	65	130	130	130	130	130	130	130
额外电路	22FET+ 1RRAM	2FeFET	2FeFET	3T+ 1FeFET	3T+ 1FeFET	2T+ 2FeFET	2T+ 2FeFET	5T+ 1FeFET
工作模式	N/A	差分	差分	单端	单端	差分	差分	单端
版图面积/μm²	N/A	59.64	48.21	53.51	52.35	61.84	61.84	57.97
控制信号个数	6	0	0	1	1	0	1	2
备份能耗/fJ	94.2	0.0	0.0	0.0	0.0	0.0	0.0	0.0
恢复能耗(0.8V)/fJ	232.40	13.10	7.33	7.31	7.74	8.21	7.65	10.76
Setup-Time(0.6V)/ps	N/A	75	65	65	65	65	65	23
Clock-to-Q(0.6V)/ps	164 @1.2 V	1164	1050	1007	995	1100	1150	760
运行功耗(0.6V)/μW	N/A	0.24	0.18	0.18	0.18	0.18	0.18	0.13
正常模式FeFET 所需开关比	N/A	NMOS管开关比	NMOS管开关比	NMOS管开关比	无影响	无影响	无影响	无影响
FeFET开关比 (3σ恢复成功率)	N/A	110	81	1.1×10⁴	1.1×10⁴	110	100	14
开关比10²温度100℃ 2000次蒙特卡洛模拟的恢复成功率	N/A	68	85	N/A	N/A	72	74	100

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