A Fast Traffic Lane Detection System Based on Parallel Processors and FPGA Implementation

Li Yuan-Jin; Zhang  Wan-Cheng; Wu  Nan-Jian

doi:10.3724/SP.J.1146.2010.00111

Volume 32 Issue 12

Jan. 2011

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Article Navigation > Journal of Electronics & Information Technology > 2010 > 32(12): 2901-2906

Li Yuan-Jin, Zhang Wan-Cheng, Wu Nan-Jian. A Fast Traffic Lane Detection System Based on Parallel Processors and FPGA Implementation[J]. Journal of Electronics & Information Technology, 2010, 32(12): 2901-2906. doi: 10.3724/SP.J.1146.2010.00111

Citation:

Li Yuan-Jin, Zhang Wan-Cheng, Wu Nan-Jian. A Fast Traffic Lane Detection System Based on Parallel Processors and FPGA Implementation[J]. Journal of Electronics & Information Technology, 2010, 32(12): 2901-2906. doi: 10.3724/SP.J.1146.2010.00111

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A Fast Traffic Lane Detection System Based on Parallel Processors and FPGA Implementation

doi: 10.3724/SP.J.1146.2010.00111 cstr: 32379.14.SP.J.1146.2010.00111

Received Date: 2010-01-28
Rev Recd Date: 2010-05-20
Publish Date: 2010-12-19

Abstract

Abstract

This paper proposes a parallel fast traffic lane detection system. The system consists of a 3232 Processing Elements (PE) array and a dual RISC core subsystem. The PE array performs pixel-parallel image preprocessing and outputs edge features, the dual RISC core subsystem performs two lanes parameters detection in parallel based on edge features. In this way, every step in the detection process is in parallel and the detection rate is rapidly increased. The system is implemented with FPGA. The experiment shows that it has good robustness and can reach up to 50 fps. This meets the demand of real-time for lane departure warning system and makes an important sense for practical application.
- Image processing,
- Traffic lane detection,
- Parallel,
- FPGA,
- RISC (Reduced Instruction Set Computer)

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References(1)

References

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