Early Detection of Instruction Data Dependence for RISC-DSP Processor

Cai Wei-Guang; Yao Qing-Dong; Liu  Peng

doi:10.3724/SP.J.1146.2010.00102

Volume 32 Issue 12

Jan. 2011

Turn off MathJax

Article Contents

Article Navigation > Journal of Electronics & Information Technology > 2010 > 32(12): 3046-3050

Cai Wei-Guang, Yao Qing-Dong, Liu Peng. Early Detection of Instruction Data Dependence for RISC-DSP Processor[J]. Journal of Electronics & Information Technology, 2010, 32(12): 3046-3050. doi: 10.3724/SP.J.1146.2010.00102

Citation:

Cai Wei-Guang, Yao Qing-Dong, Liu Peng. Early Detection of Instruction Data Dependence for RISC-DSP Processor[J]. Journal of Electronics & Information Technology, 2010, 32(12): 3046-3050. doi: 10.3724/SP.J.1146.2010.00102

Citation:

PDF( 237 KB)

Early Detection of Instruction Data Dependence for RISC-DSP Processor

doi: 10.3724/SP.J.1146.2010.00102 cstr: 32379.14.SP.J.1146.2010.00102

Received Date: 2010-01-26
Rev Recd Date: 2010-07-22
Publish Date: 2010-12-19

Abstract

Abstract

In RISC-DSP processor, the instructions with dynamic execution cycles cause difficulty to data dependence detection. Based on distributed dependence detection model, the detection operation is expressed by the calculation of the dependence relationship set. The relationship set at next cycle for each pipeline state are calculated. In the mean time, current pipeline state is detected based on the current instruction distribution and signals from each function module. Thus the instruction dependence can be determined one cycle in advance. Logic optimization based on its set operation is also proposed and implemented in our designed processor MediaDSP64. Synthesis result shows that with slight increase in hardware resource and power consumption, the detection operation can be hidden from the original pipeline critical path, and its timing delay can be decreased by about 30%.
- Signal processing,
- Instruction dependence detection,
- Pipeline technique

FullText(HTML)

References(1)

References

Lu Jia-jing, Zhou Xiao-fang, and Wang Jun-yu. A novel dynamic scheduling algorithm of data hazard for embedded processor [C]. Proceedings of the 7th IEEE International Conference on ASIC. Shanghai, China, IEEE, 2007: 28-31.[2]Chang Meng-chou and Shiau Da-sen. Design of an asynchronous pipelined processor [C]. International Conference on Communications Circuits and Systems. Seoul, Korea, IEEE, 2008: 1093-1096.[3]Shrivastava A, Earlie E, and Dutt N D, et al.. Retargetable pipeline hazard detection for partially bypassed processors [J].IEEE Transactions on Very Large Scale Integration Systems.2006, 14(8):791-801[4]余巧艳, 刘鹏. 一种面向DSP深度压缩指令的数据竞争检测方法[J]. 浙江大学学报 (工学版), 2005, 39(10): 1501-1506.Yu Qiao-yan and Liu Peng. Data hazard checking method for heavily compressed DSP instruction [J]. Journal of Zhejiang University (Engineering Science), 2005, 39(10): 1501-1506.[5]胡伟武, 张福新, 李祖松. 龙芯2号处理器设计和性能分析[J]. 计算机研究与发展, 2006, 43(6): 959-966.Hu Wei-wu, Zhang Fu-xin, and Li Zu-song. Design and performance analysis of the godson-2 processor [J].Journal of Computer Research and Development.2006, 43(6):959-966[6]MIPS Technology. MIPS32 74K Processor Core Family Software User's Manual. 2008. 12.[7]Shailender C, Robert C, and Magnus E, et al.. Simultaneous speculative threading: a novel pipeline architecture implemented in SUN's ROCK processor [C]. The 36th International Symposium on Computer Architecture. Austin, USA, IEEE, 2009: 484-495.Iqbal M A and Awan U S. Run-time reconfigurable instruction set processor design: RT-RISP [C]. The 2nd International Conference on Computer Control and Communication. Karachi, Pakistan, IEEE, 2009: 1-6.[8]Jason C, Han Guo-ling, and Zhang Zhi-ru. Architecture and compiler optimizations for data bandwidth improvement in configurable processors [J].IEEE Transactions on Very Large Scale Integration Systems.2006, 14(9):986-997[9]Shi Ce.[J].Wang Wei-dong, and Zhou Li, et al.. 32b RISC/DSP media processor: MediaDSP3201 [C]. Proceedings of SPIE-IS T Electronic Imaging. San Jose, USA, SPIE.2005,:-[10]刘鹏, 姚庆栋, 李东晓等. 32位媒体数字信号处理器[P]. 中国专利, 200410016753.8, 2007-01-31.[11]Liu Peng, Yao Qing-dong, and Li Dong-xiao, et al.. 32 bit media DSP processor [P]. China patent, 200410016753.8, 2007-01-31.

Relative Articles

Supplements(0)

Cited By

Proportional views