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Volume 30 Issue 5
Dec.  2010
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Tan Jun, Shen Qiu-shi, Wang Ling-li, Tong Jia-rong. Hierarchical Modeling and Optimization of Versatile FPGA SB[J]. Journal of Electronics & Information Technology, 2008, 30(5): 1239-1242. doi: 10.3724/SP.J.1146.2007.00787
Citation: Tan Jun, Shen Qiu-shi, Wang Ling-li, Tong Jia-rong. Hierarchical Modeling and Optimization of Versatile FPGA SB[J]. Journal of Electronics & Information Technology, 2008, 30(5): 1239-1242. doi: 10.3724/SP.J.1146.2007.00787

Hierarchical Modeling and Optimization of Versatile FPGA SB

doi: 10.3724/SP.J.1146.2007.00787 cstr: 32379.14.SP.J.1146.2007.00787
  • Received Date: 2007-05-24
  • Rev Recd Date: 2007-10-08
  • Publish Date: 2008-05-19
  • There are two restrictions in the Versatile Place and Route tool, VPR. It can only support three kinds of switch box architecture, which are Disjoint, Wilton and Universal, and the same type of wires in a channel must be distributed next to each other. To break through these two restrictions, this paper proposes a hierarchical versatile switch box model, covering arbitrary switch box architecture in FPGA. Based on this model, this paper designs new switch box architecture, JSB. Comparing with Disjoint, Wilton and Universal architecture, JSB improves greatly routability by 10.1%, 3.3% and 4.6% respectively. Furthermore, in this paper, optimizing the distribution of wires reduces the timing of critical path by 10.4% on average, compared with VPR.
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  • Fritz Mayer-Lindenberg. Design and application of a scalableembedded systems architecture with an FPGA basedoperating infrastructure. 9th Euromacro Conference onDigital System Design, Croatia, 2006: 189-196.[2]Shimizu K and Hirai S. Implementing Planar MotionTracking Algorithms on CMOS+FPGA Vision System. 2006IEEE/RSJ International Conference on Intelligent Robotsand Systems, Beijing, China, Oct. 2006: 1366-1371.[3]Spelat M, Dovis F, Girau G, and Mulassano P. A flexibleFPGA/DSP board for GNSS receivers design. Research inMicroelectronics and Electronics, [Ph. D], Politecnico diTorino, Italy, 2006: 77-80.[4]Bets V, Rose J, and Marquardt A. Architecture and CAD forDeep-submicron FPGAs, University of Toronto, KluwerAcademic Publishers, 1999. Second printing 2000: 63-103.[5]Rose J and Brown S. Flexibility of interconnection structurefor field programmable gate arrays[J].IEEE J. Solid-StateCircuits.1991, 26(3):277-282[6]Brown S, Rose J, and Vranesic Z G. A detailed router forfield-programmable gate arrays[J].IEEE Trans. on Computer-Aided Design of Integrated Circuits and System.1992, 11(5):620-628[7]Wu Y L and Marek-Sadowska M. Routing for array typeFPGAs[J].IEEE Trans. on Computer-Aided Design.1997,16(5):506-518[8]Liu Ji-ping, Fan Hong-bing, and Wu Yu-liang. On improvingFPGA routability applying multi-level switch boxes. DesignAutomation Conference, Asia and South Pacific, Kitakyushu,Japan, 21-24 Jan. 2003: 366-369.
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