Cross-Scale Functional Safety Verification: Expert-Guided Graph Learning for SoCs

BIAN Yanhao; SUN Yutao; FEI Siyang; WANG Zhijun

doi:10.11999/JEIT260719

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BIAN Yanhao, SUN Yutao, FEI Siyang, WANG Zhijun. Cross-Scale Functional Safety Verification: Expert-Guided Graph Learning for SoCs[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260719

Citation:

BIAN Yanhao, SUN Yutao, FEI Siyang, WANG Zhijun. Cross-Scale Functional Safety Verification: Expert-Guided Graph Learning for SoCs[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260719

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Cross-Scale Functional Safety Verification: Expert-Guided Graph Learning for SoCs

doi: 10.11999/JEIT260719 cstr: 32379.14.JEIT260719

School of Integrated Circuits, Beijing University of Posts and Telecommunications, Beijing 100876, China

Received Date: 2026-05-15
Accepted Date: 2026-09-15
Rev Recd Date: 2026-09-15

Available Online: 2026-09-24

Abstract

Abstract

Objective Functional safety has become a critical requirement in automotive System-on-Chip (SoC) design under ISO 26262 standards. Conventional exhaustive fault injection faces prohibitive computational costs for large-scale circuits, often resulting in missed high-risk regions or overly conservative global protection. Existing learning-based methods lack cross-scale transferability, circuit-aware inductive bias, and support for downstream hardening decisions. This work aims to provide an accurate, efficient, and transferable framework for node-level fault-criticality prediction and low-overhead selective hardening to support automotive SoC functional safety verification. Methods A standardized primitive-level fault dataset is constructed from 40 DesignWare library circuits covering four functional families: arithmetic and logic, communication and encoding, storage and control, and error correction and detection. Each circuit is converted into a unified directed graph with structural, connectivity, timing, and activity node features, and node-level criticality labels are generated via controlled stuck-at fault injection with ASIL-aware threshold calibration. An expert-guided graph learning model is proposed, which uses graph attention networks with residual connections to learn transferable fault-sensitive representations, followed by a four-layer expert rule calibration module: propagation-oriented rules emphasize high fan-out and critical-path nodes, safety-context rules highlight clock-domain crossings and reset logic, confidence-correction rules suppress false positives, and circuit-adaptive rules dynamically adjust rule intensity by functional family. An explanation-based node ranking mechanism combining structural and feature attribution analysis further forms a closed "prediction–explanation–hardening" flow for targeted protection (Fig. 1, Fig. 2). Results and Discussions Evaluated on nine benchmark circuits (gate counts 273–15,290), the method achieves up to 99.4% accuracy and outperforms GAT, CNN, and three state-of-the-art methods across all test circuits (Fig. 3, Table 4). Expert rules yield 1.77 pp accuracy improvement and 1.98 pp F1 improvement, with stronger gains in complex circuits (Fig. 7, Fig. 8). Ablation studies confirm that the four functional families provide complementary fault knowledge essential for cross-scale generalization (Fig. 4, Fig. 5). The framework achieves geometric mean 166.4× speedup over traditional fault simulation, up to 1,119× on I2C, with explainability module adding only approximately 20% overhead (Fig. 9). Selective hardening reduces area overhead by 8.35%～14.95% versus global TMR while maintaining SPFM above 99.3% and LFM above 89%. All nine circuits meet the SPFM target value associated with ASIL-D, eight circuits meet both the SPFM and LFM target values associated with ASIL-D, while the remaining circuit meets the corresponding ASIL-C target values (Fig. 10, Fig. 11). Conclusions The proposed framework enables effective cross-scale fault-criticality prediction by learning transferable patterns from primitive circuits without retraining on target designs. It achieves high accuracy, significant speedup, and low hardware overhead with ISO 26262 compliance. Future work will expand the primitive dataset coverage, adopt causal inference to reduce dependence on manually designed expert rules, and explore extension toward heterogeneous Chiplet architectures.
- Functional safety,
- Automotive System-on-Chip (SoC),
- Fault injection,
- Graph neural networks,
- Selective hardening

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References(28)

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