Communication Performance and Fault Degradation Analysis of Boundary-Interface Configurations in 2.5D Chiplet Systems

HOU Shuaikang; LIU Qinrang; LV Ping; LIU Zhengyu; XU Yuhang; LI Peijie; GUO Wei

doi:10.11999/JEIT260633

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HOU Shuaikang, LIU Qinrang, LV Ping, LIU Zhengyu, XU Yuhang, LI Peijie, GUO Wei. Communication Performance and Fault Degradation Analysis of Boundary-Interface Configurations in 2.5D Chiplet Systems[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260633

Citation:

HOU Shuaikang, LIU Qinrang, LV Ping, LIU Zhengyu, XU Yuhang, LI Peijie, GUO Wei. Communication Performance and Fault Degradation Analysis of Boundary-Interface Configurations in 2.5D Chiplet Systems[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260633

Citation:

HOU Shuaikang, LIU Qinrang, LV Ping, LIU Zhengyu, XU Yuhang, LI Peijie, GUO Wei. Communication Performance and Fault Degradation Analysis of Boundary-Interface Configurations in 2.5D Chiplet Systems[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260633

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Communication Performance and Fault Degradation Analysis of Boundary-Interface Configurations in 2.5D Chiplet Systems

doi: 10.11999/JEIT260633 cstr: 32379.14.JEIT260633

1.
Information Engineering University, Zhengzhou 450001, China
2.
National Digital Switching System Engineering & Technology Research Center, Zhengzhou 450002, China

Funds: The National Key R&D Program of China (2023YFB4404200), Science and Technology Innovation Leading Talents Subsidy Project of Central Plains (264200510020)

Received Date: 2026-05-15
Accepted Date: 2026-07-29
Rev Recd Date: 2026-07-29

Available Online: 2026-08-08

Abstract

Abstract

Objective Chiplet-based integration has emerged as an important approach for constructing large-scale heterogeneous systems. In a 2.5D chiplet system, inter-chiplet packets travel from a source node to a boundary interface in the source chiplet, traverse an interposer network, and enter the destination chiplet through a destination-side interface. Because packaging resources, micro-bump count, routing resources, and power and area budgets are limited, interfaces can be deployed only at a subset of boundary routers. Their number and distribution affect access distance, service-region formation, interface-load distribution, and traffic remapping after failures. Existing studies have addressed die-to-die standards, interposer architectures, placement, routing, simulation, and fault tolerance, but the independent structural impact of boundary-interface configuration remains insufficiently characterized. This work investigates how interface count, location, service-region partitioning, and failures affect communication performance and fault-induced degradation in 2.5D chiplet–interposer networks. Methods A graph-level structural model is developed for a 2.5D chiplet–interposer network. Each chiplet is modeled as an n×n mesh, and selected boundary routers serve as active interfaces. Each node is mapped to its nearest active interface, and nodes mapped to the same interface form a service region. Average interface-access distance, abstract end-to-end hop count, interface-load variation, maximum load ratio, and fault-induced degradation are evaluated. Three chiplet scales, n=4, 8, and 16, are considered, with interface budgets of k=2, 4, 6, k=4, 8, 12, and k=8, 16, 24, respectively. Five layouts are analyzed: Uniform-corner, Balanced-edge, Two-edge-centered, Single-edge-clustered, and Greedy-DL. Uniform, Hotspot, Transpose, Tornado, and Neighbor traffic patterns are considered. For fault analysis, each active interface is removed in turn, and affected nodes are remapped to their nearest healthy interfaces. A cycle-accurate gem5/Ruby GARNET model comprising four 4×4-mesh chiplets and a 4×4 interposer mesh is constructed. Uniform and Hotspot traffic are evaluated from 0.01 to 0.15 flits/node/cycle. The latency-based saturation injection rate is the first sampled rate at which average packet latency exceeds 50 cycles. This two-level evaluation separates structural effects from cycle-level network behavior and enables interface count, placement, traffic pattern, and fault location to be compared under consistent topology and routing assumptions for mechanism-oriented analysis. Results and Discussions Graph-level results show that increasing the number of boundary interfaces reduces average interface-access distance and abstract end-to-end hop count, while the marginal benefit diminishes as boundary coverage becomes sufficient (Fig. 3). Under a fixed interface budget, different interface locations induce distinct service-region partitions and interface-load distributions (Table 2, Fig. 4). For an 8×8 chiplet with k=8 under Uniform traffic, Greedy-DL achieves the smallest average interface-access distance of 3.125, while Balanced-edge provides a favorable compromise, with an access distance of 3.500 and a maximum load ratio of 1.250. Single-edge-clustered produces the largest access distance and abstract end-to-end hop count because its interfaces are concentrated on one boundary. Under Hotspot traffic, Two-edge-centered reduces interface-load variation to 0.016, but its access distance remains higher than those of Balanced-edge and Greedy-DL, confirming a trade-off between distance and load balance (Table 2, Fig. 5). Interface failures cause only moderate changes in average access distance but substantial load concentration at the remaining healthy interfaces. Under Hotspot traffic, the worst maximum-load-ratio degradation is 23.94% for Balanced-edge and 93.75% for both Two-edge-centered and Single-edge-clustered (Table 3), indicating that vulnerability is governed mainly by service-region migration and load reconcentration.The gem5 results further support the graph-level observations. When the interface count increases from k=1 to k=4, low-load latency decreases from 24.50/24.44 cycles to 18.05/18.09 cycles under Uniform and Hotspot traffic, respectively, while the latency-based saturation injection rate increases from 0.06 to 0.14 (Fig. 6). Across the k=4 layouts, Balanced-edge achieves low latency and hop count, whereas Single-edge-clustered has the highest baseline cost. Under Hotspot traffic, Balanced-edge reduces low-load latency by about 14.3% and average hop count by about 18.7% compared with Single-edge-clustered. Greedy-DL provides short low-load paths, but its saturation injection rate is 0.13, lower than the 0.14 achieved by Balanced-edge and several other layouts, showing that minimizing access distance alone does not guarantee stronger medium- and high-load behavior (Fig. 7). For fault validation, all 16 single-interface failure locations are traversed for each of three layouts, yielding 48 scenarios. The results show increases in latency and hop count, together with an earlier onset of congestion. The worst-case latency-based saturation injection rate decreases to 0.10–0.11, and Balanced-edge exhibits smaller average and worst-case degradation than the more concentrated layouts (Fig. 8, Table 5). Conclusions Boundary-interface configuration is a key structural parameter in 2.5D chiplet interconnect design. It affects interface-access distance, service-region formation, interface-load distribution, and fault-induced traffic remapping. Increasing interface count improves communication efficiency, but with diminishing benefit. Under the same interface budget, interface placement determines whether traffic remains balanced or becomes concentrated after mapping and remapping. The graph-level metrics support low-cost screening and mechanism analysis, while gem5/Ruby GARNET simulations provide cycle-accurate validation under buffering, arbitration, and flow-control effects. Therefore, interface count, location, load balance, and fault degradation should be evaluated jointly in 2.5D chiplet–interposer network design.
- Chiplet,
- interposer network,
- inter-chiplet interconnect,
- boundary interface,
- fault remapping

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References(26)

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