A Parametric Architecture Description Framework for Embedded FPGAs and Multi-objective QoR-driven Architecture Exploration

ZHOU Jing; ZHANG Shengbing; CHEN Lei; FENG Hanxu; WANG Shuo; TIAN Chunsheng

doi:10.11999/JEIT260609

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ZHOU Jing, ZHANG Shengbing, CHEN Lei, FENG Hanxu, WANG Shuo, TIAN Chunsheng. A Parametric Architecture Description Framework for Embedded FPGAs and Multi-objective QoR-driven Architecture Exploration[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260609

Citation:

ZHOU Jing, ZHANG Shengbing, CHEN Lei, FENG Hanxu, WANG Shuo, TIAN Chunsheng. A Parametric Architecture Description Framework for Embedded FPGAs and Multi-objective QoR-driven Architecture Exploration[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260609

Citation:

ZHOU Jing, ZHANG Shengbing, CHEN Lei, FENG Hanxu, WANG Shuo, TIAN Chunsheng. A Parametric Architecture Description Framework for Embedded FPGAs and Multi-objective QoR-driven Architecture Exploration[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260609

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A Parametric Architecture Description Framework for Embedded FPGAs and Multi-objective QoR-driven Architecture Exploration

doi: 10.11999/JEIT260609 cstr: 32379.14.JEIT260609

1.
Northwestern Polytechnical University, Xi’an 710072, China
2.
Beijing Microelectronics Technology Institution, Beijing 100070, China

Accepted Date: 2026-07-29
Rev Recd Date: 2026-07-29

Available Online: 2026-08-08

Abstract

Abstract

Objective Architecture parameters of Commercial off-the-shelf Field Programmable Gate Arrays (FPGAs) are fixed by the vendor and reused across products. Embedded FPGAs (eFPGAs) leave that choice to the architect, so the LUT input size K, the cluster size N, the interconnect topology, and the heterogeneous tiles are all configurable for the target application. This makes architecture exploration a task in design flow, where tens to hundreds of architectures may have to be drafted and compared before one is settled on. The way architectures are described today holds such exploration back: every architecture is written out by hand and re-aligned across the architecture files of multiple backend toolchains after each parameter change, no formal model keeps these files consistent, and measured QoR data spanning real application domains and heterogeneous tile combinations are rarely shared. To loosen these frictions, the work reported here treats eFPGA architecture description as a research object. The description is given a typed form on which multi-view generation and field-level checking are formally defined, and this model is realized as an open framework that drives the mainstream backend toolchains from one source description. A parameter-sweep design space exploration is then carried out on the framework, and a multi-domain QoR dataset is released alongside as a public benchmark. Methods HorizonArch, the parametric framework proposed in this work, organizes architecture parameters into three independence layers (Table 1). L0 captures process invariants that depend only on the technology node; L1 holds coupled parameters such as K, N, segment length, switch block type, and channel connectivity, where one change forces updates across many fields in the architecture files of different backend toolchains; and L2 holds independent parameters that the architect can set on their own. Architecture construction is formalized as one operator B that maps a parameter vector p to a complete architecture object (Fig. 4), governed by five formal rules: parameter completeness (R1), fragment independence (R2), type compatibility (R3), explicit coupling (R4), and static checkability (R5). Each backend artifact is then produced by an independent derivation function that consumes the same source object, so adding a new tool requires only one new view rather than edits across all existing ones. Field-level validation runs at load time, and cross-field references are checked before any backend is invoked. The class structure (Fig. 3) splits the architecture into synthesis, circuit, and layout views, with each semantic element declared only once. Three extension levels keep the framework open: G1 adds a black-box module, G2 enlarges the value set of an existing coupled parameter, and G3 introduces a new coupled parameter together with its constrained value set. Built on this framework, a parameter-sweep design space exploration method scans the (K, N) grid and the heterogeneous tile combinations, and assesses each configuration using three QoR metrics: area, critical-path delay (CPD), and area-delay product (ADP), where ADP is a derived composite metric calculated from area and CPD. Results and Discussions End-to-end validation confirms that one source description drives VPR, OpenFPGA, and Yosys consistently; COFFE is validated through interface integration and SPICE startup (Table 4, Table 5), and the G1, G2, and G3 extension experiments all pass the cross-field checks. The design space exploration study then reveals a clear divergence among the three QoR metrics on the (K, N) plane (Fig. 5, Fig. 6). Area is dominated by K and favors small K, and most circuits place their area optimum at K=4 N=4. CPD, in contrast, is mildly negatively correlated with both K and N, and its optimum clusters near (8, 10) and (7, 10). The relative range across the twenty (K, N) points (Table 7) is much larger for area and ADP than for CPD, so parameter choice gives a much bigger lever on cost than on raw delay. A study of default configurations (Table 8) shows that K=4 N=4 reaches the per-circuit ADP optimum on 68% of circuits and stays within about six percent on average, while its CPD deviates by close to fifty percent; K=8 N=10 takes the opposite role, with its CPD deviation cut to 5.9% and 30.8% of circuits hit exactly, but its area and ADP deviations soar past 670% and 480%. A random-forest cross-domain surrogate reaches about 65% top-5 accuracy, so a parameter sweep is still needed when the design target is tight. Conclusions This work presents HorizonArch, a formal multi-backend parametric architecture description framework for eFPGA exploration. The framework drives VPR, OpenFPGA, and Yosys from one source description and exposes an extensible COFFE interface. The parameter-sweep exploration carried out on the framework shows that area and CPD favor opposite directions in the (K, N) plane, which means eFPGA architecture parameters should be chosen against an explicit design target rather than a default value. An open QoR dataset covering five application domains is released alongside as a public benchmark. Future work will complete the COFFE SPICE rewriting component, refit the routing-area coefficient with measured data, and explore more efficient exploration strategies on top of the framework.

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References(16)

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