A Reconfigurable Parallelised Coprocessor Design for the RISC-V-Based Grain Cryptographic Algorithm

NAN Longmei; WANG Haoyu; DU Yiran; LI Wei; CHEN Tao

doi:10.11999/JEIT260391

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NAN Longmei, WANG Haoyu, DU Yiran, LI Wei, CHEN Tao. A Reconfigurable Parallelised Coprocessor Design for the RISC-V-Based Grain Cryptographic Algorithm[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260391

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NAN Longmei, WANG Haoyu, DU Yiran, LI Wei, CHEN Tao. A Reconfigurable Parallelised Coprocessor Design for the RISC-V-Based Grain Cryptographic Algorithm[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260391

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A Reconfigurable Parallelised Coprocessor Design for the RISC-V-Based Grain Cryptographic Algorithm

doi: 10.11999/JEIT260391 cstr: 32379.14.JEIT260391

College of Cryptography Engineering, Information Engineering University, Zhengzhou 450000, China

Received Date: 2026-04-01
Accepted Date: 2026-07-28
Rev Recd Date: 2026-07-28

Available Online: 2026-08-07

Abstract

Abstract

Objective To overcome the performance bottleneck of Grain cryptographic algorithms on general-purpose processors (GPPs), as well as the inflexibility and high overhead of application-specific inte-grated circuit (ASIC) implementations, this work integrates dedicated cryptographic hardware accel-erators into a RISC-V coprocessor via a custom instruction extension approach. A reconfigurable and parallelisable implementation architecture is proposed specifically for the Grain algorithm family, lev-eraging the RISC-V coprocessor interface. Corresponding custom instructions are designed to enable flexible and efficient execution of Grain-80, Grain-128, Grain-128a, and Grain-128AEAD on the same hardware platform. The proposed architecture achieves a favourable trade-off between processing throughput and hardware flexibility, making it suitable for resource-constrained embedded systems. Methods This paper employs a unified feedback shift register architecture to support flexible swi-tching between the Grain-80, Grain-128, and Grain-128a, Grain-128AEAD algorithms, while enabling parallelisation granularity to be flexibly configured between 1 and 8 steps, thereby further enhancing throughput and resource utilisation, When extending specialised instructions for the Grain cryptogra-phic algorithm, the software and hardware functional modules are analysed, dividing the entire crypt-ographic process into software and hardware components to efficiently complete the encryption proc-edure. The coprocessor implementation proposed in this study features a streamlined architecture, ac-hieving reconfigurable parallel realisations of all four Grain algorithms with minimal hardware resou-rce expansion. Results and Discussions By invoking specialised instructions for the reconfigurable parallelised Grain cryptographic algorithm, three distinct cryptographic algorithms can be flexibly implemented. Comp-aring results with nonextended instructions (Table 7) demonstrates that specialised instructions enh-ance both the execution rate of cryptographic algorithms and reduce the number of required instruc-tions. Contrasting with results from other literature (Table 8) reveals the advantages of this approach in resource reuse and design flexibility. Compared to purely software implementations, this approach achieves significant optimisation in both the number of executed instructions and the number of ope-rational cycles. When contrasted with general-purpose reconf-igurable hardware implementations, this solution demonstrates superior resource utilisation. Conclusions To address the demand for agile deployment and resource-efficient implementation of cryptographic algorithms in lightweight embedded systems, this paper designs a hardware-software co-operative, reconfigurable parallelisation scheme for accelerating the Grain cryptogra-phic algorith-m. This approach leverages the RISC-V coprocessor instruction extension mechanism. Through a unif-ied shift register architecture, configurable feedback tap selection network, and feedback logic tailored for a deterministic algorithm set, the solution enables dynamic switching and parallel processing of four algorithms—Grain-80, Grain-128, Grain-128a and Grain-128AEAD—on a single hardware platfo-rm. This approach effectively reduces hardware resource consumption while maintaining functional flexibility. The present work primarily focuses on the reconfigurable parallelisation of the Grain algor-ithm family. Future research will explore universal reconfigurable architectures for nonlinear Boolean functions, incorporating reconfigurable units such as lookup tables (LUTs) or programmable logic ar-rays. By flexibly adapting to multiple stream cipher algorithms through configuration information, th-is approach aims to enhance algorithm compatibility and scalability within hardware modules while maintaining high throughput and low resource overhead.
- RISC-V,
- coprocessor,
- instruction extension,
- Grain cryptographic algorithm,
- reconfigura-ble parallelisation

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References(17)

References

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