Design of LDPC Decoding Based on a Domestic NPU

WANG Tiansheng; HAN Kaifeng; CHEN Li; DU Ying

doi:10.11999/JEIT260172

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WANG Tiansheng, HAN Kaifeng, CHEN Li, DU Ying. Design of LDPC Decoding Based on a Domestic NPU[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260172

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WANG Tiansheng, HAN Kaifeng, CHEN Li, DU Ying. Design of LDPC Decoding Based on a Domestic NPU[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260172

WANG Tiansheng, HAN Kaifeng, CHEN Li, DU Ying. Design of LDPC Decoding Based on a Domestic NPU[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260172

Citation:

WANG Tiansheng, HAN Kaifeng, CHEN Li, DU Ying. Design of LDPC Decoding Based on a Domestic NPU[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260172

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Design of LDPC Decoding Based on a Domestic NPU

doi: 10.11999/JEIT260172 cstr: 32379.14.JEIT260172

WANG Tiansheng^1
,,
HAN Kaifeng^{2
,
,},
CHEN Li^1
,,
DU Ying^2
,

1.
Department of Electronic Engineering and Information Science, University of Science and Technology of China, Hefei 230026, China
2.
China Academy of Information and Communications Technology, Institute of Wireless and Mobile Communications, Beijing 100191, China

Funds: The National Science Foundation for Young Scientists of China (62522126), The General Program of the National Natural Science Foundation of China (62471449), The National Science Foundation of China (U25A20394)

Received Date: 2026-02-09
Accepted Date: 2026-10-28
Rev Recd Date: 2026-10-28

Available Online: 2026-10-31

Abstract

Abstract

Objective Sixth-Generation (6G) mobile communication represents a new generation of intelligent, integrated digital information infrastructure that combines communication, sensing, computation, and intelligence. As a core component of 6G wireless access networks, the base station is evolving into an intelligent edge service node that integrates communication, computation, and Artificial Intelligence (AI) services. Therefore, domestic AI accelerators, such as Neural Processing Units (NPUs), are increasingly being integrated into base station architectures. Deploying communication physical-layer tasks and AI services on a unified NPU-based platform provides an effective approach to improving hardware resource utilization. However, Low-Density Parity-Check (LDPC) decoding, a key physical-layer technique, requires irregular and noncontiguous memory access because of its sparse graph structure. These access patterns are poorly suited to the tensor-centric computational architecture of NPUs, making efficient deployment difficult. To address this mismatch, a fully tensorized parallel LDPC decoding framework, termed DaVinci-LDPC, is proposed for the DaVinci architecture of Huawei Ascend NPUs. Methods Three optimization strategies are developed to adapt irregular sparse-graph computations to tensor-based hardware. First, a static graph topology mapping mechanism is constructed to transform factor graph connections into fixed tensor indices, reducing runtime dynamic branching and control-flow overhead. Second, a Dual-Gather message-passing strategy is proposed to address memory bandwidth bottlenecks caused by random memory access. This strategy uses the NPU’s vector processing units to efficiently handle message exchange between variable nodes and check nodes. Finally, a vectorized hyperbolic tangent operator fusion scheme is designed for the Sum-Product Algorithm (SPA) to address the difficulty of vectorizing nonlinear operations and the risk of numerical overflow in 16-bit Floating-Point (FP16) calculations. This scheme enables highly parallel check-node updates while maintaining numerical stability. Results and Discussions The performance of the DaVinci-LDPC framework is evaluated against a multithreaded Central Processing Unit (CPU) baseline, and its decoding accuracy is assessed against practical communication requirements. The NPU implementation uses FP16 SPA decoding, whereas the CPU baseline uses the 32-bit Floating-Point (FP32) Normalized Min-Sum (NMS) algorithm. Experimental results show that the NPU implementation achieves a Bit Error Rate (BER) of approximately 10^–7 at a Signal-to-Noise Ratio (SNR) of 3.5 dB for a code length of 2048 bits (Fig. 4), below the BER level of 10^–5 cited as a practical requirement in the study. Although the NPU implementation exhibits a higher BER than the CPU baseline at higher SNRs, it achieves the stated BER target under the tested conditions. In terms of throughput, the NPU implementation achieves increasing performance advantages as the code length increases (Table 2, Fig. 5). At a code length of 4096 bits, its throughput reaches 134.2 Mbps, compared with 9.5 Mbps for the CPU baseline, corresponding to a reported peak speedup of 14.09 times under the respective test configurations (Table 2). Conclusions An efficient parallel LDPC decoding system is designed and implemented on the domestic Huawei Ascend NPU platform, demonstrating its acceleration capabilities for 5G/6G physical-layer algorithms. Through static graph topology mapping, Dual-Gather message passing, and vectorized operator fusion, the DaVinci-LDPC framework addresses the structural mismatch between sparse LDPC factor graphs and the DaVinci tensor architecture. The resulting system achieves high throughput and numerical stability while satisfying the stated decoding accuracy requirements under the tested conditions. These findings demonstrate the feasibility of using domestic NPUs for conventional communication physical-layer decoding and provide a reference for the future development of AI-native, software-defined 6G physical-layer systems.
- LDPC codes,
- Ascend NPU,
- DaVinci Architecture,
- Parallel computing

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References(28)

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