Performance Optimization and Gate Oxide Electric Field Analysis of 1200V Trench SiC MOSFET Based on PCL-CSL Collaborative Design

FANG Shaoming; LI Hongda; GAO Yuan

doi:10.11999/JEIT260164

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FANG Shaoming, LI Hongda, GAO Yuan. Performance Optimization and Gate Oxide Electric Field Analysis of 1200V Trench SiC MOSFET Based on PCL-CSL Collaborative Design[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260164

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FANG Shaoming, LI Hongda, GAO Yuan. Performance Optimization and Gate Oxide Electric Field Analysis of 1200V Trench SiC MOSFET Based on PCL-CSL Collaborative Design[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260164

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Performance Optimization and Gate Oxide Electric Field Analysis of 1200V Trench SiC MOSFET Based on PCL-CSL Collaborative Design

doi: 10.11999/JEIT260164 cstr: 32379.14.JEIT260164

1.
Shenzhen Jinyu Semiconductor Co., Ltd., Shenzhen 518000, China
2.
Southern University of Science and Technology, Shenzhen 518055, China

Funds: Shenzhen Science and Technology Program (KJZD20240903104021027)

Received Date: 2026-02-09
Accepted Date: 2026-04-17
Rev Recd Date: 2026-04-16

Available Online: 2026-04-30

Abstract

Abstract

Objective SiC trench MOSFETs at 1200 V rating are widely recognized as key components in modern medium- and high-voltage power conversion systems due to their superior switching performance, low conduction loss, and high-temperature stability. However, conventional trench-based device structures suffer from severe electric field crowding at the trench corner and bottom gate oxide, which frequently causes the peak oxide electric field to exceed the safe operating limit of 3 MV/cm and seriously threatens long-term reliability. Moreover, significant performance trade-offs exist among breakdown voltage, specific on-resistance, threshold voltage, and gate oxide electric field, so it is difficult to achieve high efficiency and high robustness simultaneously. To overcome these bottlenecks, a synergistic structure combining deep P-type columns (PCL), Carrier Storage Layer (CSL), and locally thickened gate oxide is investigated in this work. The primary objective is to modulate the electric field distribution, suppress electric field concentration, improve carrier transport behavior, and realize a well-balanced device performance. This study aims to provide a systematic and practical design methodology for the development of high-reliability, high-performance 1200 V SiC trench MOSFETs for industrial applications. Methods Numerical device simulations are systematically performed using the TCAD simulation platform to comprehensively analyze and optimize the electrical performance of 1200 V SiC trench MOSFETs. To ensure simulation results, a full set of advanced physical models is rigorously implemented, including bandgap narrowing, Shockley-Read-Hall (SRH) recombination, Auger recombination, impact ionization for avalanche breakdown, incomplete ionization of dopants, and high-field saturation mobility models accounting for velocity saturation and scattering effects. A device structure integrated with deep PCL, CSL, and locally thickened bottom gate oxide is constructed to suppress the gate oxide electric field and improve device reliability. Key structural and process parameters are systematically swept and quantitatively analyzed, including epitaxial layer thickness and doping concentration, trench width and depth, P-well implantation dose, PCL spacing, and CSL implantation dose. Static electrical characteristics, such as threshold voltage (V_th), specific on-resistance (R_on,sp), breakdown voltage (BV), and peak gate oxide electric field (E_ox,max) are extracted and evaluated. The optimal parameter combination is finally determined through a comprehensive trade-off analysis between conduction performance and long-term device reliability, achieving a balanced performance for high-power applications. Results and Discussions Simulation results demonstrate that the deep PCL structure effectively redirects electric field lines away from the trench bottom gate oxide and significantly alleviates electric field crowding. Combined with locally thickened bottom gate oxide, the peak gate oxide electric field is reduced to below 3 MV/cm, which satisfies industrial reliability standards. The introduction of the CSL layer broadens the vertical conduction path, relieves current crowding, and effectively reduces specific on-resistance. Parameter optimization reveals that epitaxial conditions, trench dimensions, PW implantation doses and CSL implantation doses directly determine the trade-off between breakdown voltage and conduction performance (Fig. 5, Fig. 6, Fig. 9, Fig. 10, Fig. 19), while PCL spacing exhibits a significant influence on electric field shielding (Fig. 16, Fig. 17). After multi-parameter optimization, the device achieves a threshold voltage of 4.7 V, a high breakdown voltage of 1708 V, a low specific on-resistance of 1.57 mΩ·cm², and a safe gate oxide peak field of 2.5 MV/cm (Table 2), demonstrating excellent overall performance suitable for high-voltage power applications. Conclusions A synergistic PCL-CSL structural design for 1200 V SiC trench MOSFETs is researched and validated through TCAD simulation. To address the inherent bottlenecks of conventional SiC trench MOSFETs, such as high gate oxide electric field, restricted breakdown capability and contradictory trade-off between on-state conduction loss and device reliability, the modulation mechanism of deep PCL and CSL is comprehensively explored. The influences of epitaxial layer thickness and doping level, trench dimensions, P-well implantation doses, PCL spacing, and CSL implantation doses on key electrical performance and gate oxide long-term reliability are systematically clarified and summarized through extensive parameter sweeping and comparative analysis.Under the collaborative optimization of multiple structural factors, the optimized device configuration achieves a superior comprehensive performance balance, including low specific on-resistance for reduced conduction loss, high and stable breakdown voltage for high-voltage endurance, reasonable threshold voltage for normal switching operation, and suppressed electric field concentration near the trench bottom oxide. Benefiting from the rational doping profile and structural arrangement, the peak gate oxide electric field is effectively limited and steadily controlled below the 3 MV/cm industrial safety threshold, which greatly prevents oxide degradation and guarantees stable and robust device operation under high-bias and harsh working conditions.The structural strategy and parameter optimization method provide valuable guidance for the design, simulation, and process development of high-voltage and high-reliability SiC power devices. This work contributes to the performance improvement of wide-bandgap semiconductor devices and promotes their industrial application in renewable energy systems, electric vehicles, and medium-voltage power supplies.
- Silicon Carbide,
- Trench MOSFET,
- Device design,
- Electrical properties,
- Peak electric field in gate oxide

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References(20)

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