V-Agent: A Protocol-Driven Multi-Agent Framework for RISC-V Custom Arithmetic IP Integration

LI Tuo; WANG Changhong; CHENG Chao; LI Guoqing; LI Nanjun

doi:10.11999/JEIT260073

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LI Tuo, WANG Changhong, CHENG Chao, LI Guoqing, LI Nanjun. V-Agent: A Protocol-Driven Multi-Agent Framework for RISC-V Custom Arithmetic IP Integration[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260073

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LI Tuo, WANG Changhong, CHENG Chao, LI Guoqing, LI Nanjun. V-Agent: A Protocol-Driven Multi-Agent Framework for RISC-V Custom Arithmetic IP Integration[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT260073

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V-Agent: A Protocol-Driven Multi-Agent Framework for RISC-V Custom Arithmetic IP Integration

doi: 10.11999/JEIT260073 cstr: 32379.14.JEIT260073

1.
Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co., Ltd., Jinan 250000, China
2.
Jinan Maxwell Smart Technology Co., Ltd., Jinan 250000, China

Accepted Date: 2026-09-17
Rev Recd Date: 2026-09-17

Available Online: 2026-09-24

Abstract

Abstract

Objective Large language models (LLMs) can assist register-transfer-level (RTL) generation, but processor-level designs require coordination among independently generated control, datapath, top-level, and verification modules. Inconsistent port names, directions, widths, or signal types can block compilation and make repair dependent on manual diagnosis. V-Agent is proposed as a protocol-driven multi-agent framework that converts such interface assumptions into explicit, machine-checkable contracts and routes tool diagnostics back to the responsible generator. Four specialized agents handle architecture specification, control logic, datapath integration, and verification. A single-cycle RISC-V processor integrating a predefined 32-bit signed combinational multiplier IP is used as a controlled task to evaluate multi-module generation, localized error correction, and differences among LLM backends. The workflow therefore targets the integration gap between isolated code generation and executable processor-level verification, with emphasis on whether structural assumptions can be exposed early enough to support bounded, module-local regeneration. Methods V-Agent receives a hierarchical JavaScript Object Notation (JSON) configuration containing the selected LLM backend, generation and retry parameters, architecture attributes, task operations, data widths, and test cases. The Architect Agent generates top-level ports, control signals, datapath components, and operation-code mappings; the Control Unit Agent produces synthesizable decoding and control logic; the Datapath Agent generates arithmetic, register-file, program-counter, routing, and top-level integration logic and instantiates the fixed multiplier IP; and the Verification Agent produces memory models, testbenches, Verilator drivers, and execution scripts. The processor and accelerator organization is shown in Fig. 1, and the multi-agent and verification feedback loops are summarized in Figs. 2 and 3. Port names, directions, widths, and types are recorded in JSON interface contracts. A static analyzer parses the Verilog abstract syntax tree (AST) and compares generated port signatures with the contracts. Compilation and simulation add syntax, connection, and functional diagnostics. Failed checks are returned to the responsible agent and trigger regeneration, with max_retries set to 3. A fallback template is used only when repeated generation reaches the retry limit, allowing the remaining integration and verification steps to continue. The task implements two standard instructions and three experimental custom operations, MLOAD, PMUL, and PMAC. Six LLM backends—DeepSeek-V3, Claude Sonnet 4.5, Doubao-1.5 Pro, Gemini 1.5 Flash, Qwen3-235B, and GPT-5.1—are evaluated using module compilation, automatic tests, Code Quality Score, line-level repair changes, and backend power-performance-area (PPA) outputs. Fully automated results are recorded before manual modification, whereas human-in-the-loop (HITL) results are measured after localized repair. Results and Discussions The monolithic one-shot baseline outputs fail system-level compilation because of context, interface, connection, or incomplete-state-logic problems, whereas the V-Agent pipeline produces samples that can enter system-level compilation (Table 4). This observation is limited to the present benchmark. In fully automated evaluation, DeepSeek-V3 and Claude-4.5 complete all five task operations, compile all eight RTL modules, and pass 70 of 78 automatic tests (Table 6). Doubao-Pro and Gemini-Flash compile 6 of 8 modules, GPT-5.1 compiles 7 of 8, and Qwen3-235B compiles 4 of 8. Because executable automatic-test workloads differ among generated outputs, raw counts and denominators are retained rather than treated as a uniform benchmark; completion and test-pass ratios are shown in Fig. 4. A width-mismatch case demonstrates the feedback mechanism: the Datapath Agent initially generates a one-bit MemToReg signal, while the additional multiplier result path requires a two-bit selector. Contract checking identifies the mismatch, returns the diagnostic to the responsible agent, and completes regeneration in approximately 15 s before compilation and testing pass (Table 7). In the complete case study, the four agents generate eight RTL modules and 17 verification files in about 5 min; all eight modules compile, and four system-level programs produce the expected final register states and waveforms. The generated arithmetic execution and writeback path is shown in Fig. 5. After localized HITL edits, all six designs compile 8 of 8 modules and pass the same 78 tests. The average line-level code-change rate is 4.37%, ranging from 1.3% to 9.5% (Table 9). Backend analysis shows that Claude, DeepSeek, and Gemini complete synthesis and timing analysis, while GPT-5.1 does not converge because of a combinational loop and the unusually small Doubao and Qwen implementations exhibit synthesis pruning (Table 8). Among 126 classified generation- and compilation-stage errors, 54 are Verilog semantic errors, 36 are interface-width errors, 26 are cascading failures, and 10 are custom-operation semantic errors (Table 10). Conclusions V-Agent organizes processor RTL generation as cooperation among specialized agents connected by explicit interface contracts and tool feedback. The evaluated RISC-V arithmetic-IP task shows that structural interface mismatches can be localized and corrected without regenerating the complete design, while HITL results separate initial generation quality from engineering repairability. The principal contribution is a coordination mechanism that turns cross-module assumptions into checkable contracts and returns AST, compilation, and simulation diagnostics to the responsible generator, rather than a replacement for established synthesis, simulation, high-level synthesis, or verification tools. The evidence is limited to a single-cycle RISC-V core, a fixed 32-bit multiplier IP, 5–15 task operations, and nonuniform executable test workloads. Verilator cannot expose every timing defect, and the PPA study requires more complete activity, supply, and netlist conditions. Future work will extend the workflow to pipelined processors and coverage-guided automated repair.
- Multi-Agent Systems,
- Large language models,
- RISC-V,
- Arithmetic IP Integration

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References(30)

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