Advanced Search
Turn off MathJax
Article Contents
JIANG Danping, DAI Zibin, LIU Yanjiang, ZHOU Zhaoxu, SONG Xiaoyu. Bayesian Optimization-Driven Design Space Exploration Method for Coarse-Grained Reconfigurable Cipher Logic Array[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250624
Citation: JIANG Danping, DAI Zibin, LIU Yanjiang, ZHOU Zhaoxu, SONG Xiaoyu. Bayesian Optimization-Driven Design Space Exploration Method for Coarse-Grained Reconfigurable Cipher Logic Array[J]. Journal of Electronics & Information Technology. doi: 10.11999/JEIT250624

Bayesian Optimization-Driven Design Space Exploration Method for Coarse-Grained Reconfigurable Cipher Logic Array

doi: 10.11999/JEIT250624 cstr: 32379.14.JEIT250624
Funds:  The National Natural Science Foundation of China (62302519)
  • Received Date: 2025-07-03
  • Rev Recd Date: 2025-10-21
  • Available Online: 2025-10-24
  •   Objective  Coarse-Grained Reconfigurable Cipher Logic Arrays (CGRCAs) are widely employed in information security systems owing to their high flexibility, strong performance, and inherent security. Design Space Exploration (DSE) plays a critical role in evaluating and optimizing the performance of cryptographic algorithms deployed on CGRCAs. However, conventional DSE approaches require extensive computation time to locate optimal solutions in multi-objective optimization problems and often yield suboptimal performance. To overcome these limitations, this study proposes a Bayesian optimization-based DSE framework, termed Multi-Objective Bayesian Optimization-based Exploration (MOBE), which enhances search efficiency and solution quality while effectively satisfying the complex design requirements of CGRCA architectures.  Methods  The high-dimensional characteristics and multi-objective optimization features of the CGRCA are analyzed, and its design space is systematically modeled. A DSE method based on Bayesian optimization is then proposed, comprising initial sampling design, rapid evaluation model construction, surrogate model development, and acquisition function optimization. A knowledge-aware unsupervised learning sampling strategy is introduced to integrate domain-specific knowledge with clustering algorithms, thereby improving the representativeness and diversity of the initial samples. A rapid evaluation model is established to estimate throughput, area overhead, and Function Unit (FU) utilization for each sample, effectively reducing the computational cost of performance evaluation. To enhance both search efficiency and generalizability, a greedy-based hybrid surrogate model is constructed by combining Gaussian Process with Deep Kernel Learning (DKL-GP), random forest, and neural network models. Moreover, an adaptive multi-acquisition function is designed by integrating Expected Hyper Volume Improvement (EHVI) and quasi-Monte Carlo Upper Confidence Bound (qUCB) to identify the most promising samples and maintain a balanced trade-off between exploration and exploitation. The weighting ratio between EHVI and qUCB is dynamically adjusted to accommodate the varying optimization requirements across different search phases.  Results and Discussions  The DSE method based on Bayesian optimization (Algorithm 2) includes initial sampling design, rapid evaluation model construction, surrogate model development, and acquisition function optimization to enhance solution quality and search efficiency. Simulation results show that the knowledge-aware unsupervised learning sampling strategy reduces the Average Distance from Reference Set (ADRS) by up to 28.2% and increases hypervolume by 15.1% compared with existing sampling approaches (Table 3). This improvement primarily arises from the integration of domain knowledge with clustering algorithms. Compared with single surrogate model–based DSE methods, the greedy-based hybrid surrogate model leverages the complementary advantages of multiple surrogate models across different optimization stages, prioritizing samples that contribute most to hypervolume expansion. The hybrid surrogate model achieves a reduction in ADRS of up to 31.7% and an improvement in hypervolume of 20.0% (Table 4). Furthermore, the proposed MOBE framework achieves a 34.9% reduction in ADRS and increases hypervolume by 28.7% relative to state-of-the-art DSE methods (Table 5). Regarding the average performance metrics of Pareto-front samples, MOBE enhances throughput by up to 29.9%, reduces area overhead by 6.0%, and improves FU utilization by 11.6% (Fig. 6), confirming its superiority in overall solution quality. Moreover, the MOBE method exhibits excellent cross-algorithm stability in both hypervolume and Normalized Overall Execution Time (NOET) (Fig. 7 and Table 6).  Conclusions  This study presents a multi-objective DSE method based on Bayesian optimization that enhances both solution quality and search efficiency for CGRCA. The proposed approach employs a knowledge-aware unsupervised learning sampling strategy to generate an initial sample set with high representativeness and diversity. A rapid evaluation model is subsequently developed to reduce the computational cost of performance assessments. Additionally, the integration of adaptive multi-acquisition functions with a greedy-based hybrid surrogate model further improves the efficiency and generalization capability of the DSE framework. Comparative experiments demonstrate the effectiveness of the proposed MOBE method: (1) the sampling strategy reduces the ADRS by up to 28.2% and increases hypervolume by 15.1% compared with existing methods; (2) the greedy-based hybrid surrogate model achieves up to a 31.7% reduction in ADRS and a 20.0% improvement in hypervolume relative to single surrogate model–based approaches; (3) the overall MOBE framework achieves a 34.9% reduction in ADRS and a 28.7% increase in hypervolume compared with state-of-the-art DSE techniques; (4) MOBE improves throughput by up to 29.9%, reduces area overhead by 6.0%, and increases FU utilization by 11.6% relative to existing methods; and (5) MOBE exhibits excellent cross-algorithm stability in hypervolume and NOET. MOBE is applicable to medium-and-high-performance cryptographic application scenarios, including cloud platforms and desktop terminals. Nevertheless, two limitations remain. First, MOBE currently employs only traditional surrogate models, which may constrain feature learning efficiency and modeling accuracy. Second, its validation is confined to a CGRCA architecture previously developed by the research group, lacking verification across existing CGRCA architectures. Future work will address these limitations by incorporating emerging artificial intelligence techniques, such as large models, and conducting extensive experiments on diverse CGRCA architectures to further enhance the generalization and effectiveness of MOBE.
  • loading
  • [1]
    DESHWAL A, JAYAKODI N K, JOARDAR B K, et al. MOOS: A multi-objective design space exploration and optimization framework for NoC enabled manycore systems[J]. ACM Transactions on Embedded Computing Systems (TECS), 2019, 18(5s): 77. doi: 10.1145/3358206.
    [2]
    KIRKPATRICK S, GELATT JR C D, and VECCHI M P. Optimization by simulated annealing[J]. Science, 1983, 220(4598): 671–680. doi: 10.1126/science.220.4598.671.
    [3]
    DEB K, PRATAP A, AGARWAL S, et al. A fast and elitist multiobjective genetic algorithm: NSGA-II[J]. IEEE Transactions on Evolutionary Computation, 2002, 6(2): 182–197. doi: 10.1109/4235.996017.
    [4]
    ZHANG Qingfu and LI Hui. MOEA/D: A multiobjective evolutionary algorithm based on decomposition[J]. IEEE Transactions on Evolutionary Computation, 2007, 11(6): 712–731. doi: 10.1109/TEVC.2007.892759.
    [5]
    WENG Jian, LIU Sihao, DADU V, et al. DSAGEN: Synthesizing programmable spatial accelerators[C]. 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture, Valencia, Spain, 2020: 268–281. doi: 10.1109/ISCA45697.2020.00032.
    [6]
    TAN Cheng, XIE Chenhao, LI Ang, et al. AURORA: Automated refinement of coarse-grained reconfigurable accelerators[C]. 2021 Design, Automation & Test in Europe Conference & Exhibition, Grenoble, France, 2021: 1388–1393. doi: 10.23919/DATE51398.2021.9473955.
    [7]
    BANDARA T K, WIJERATHNE D, MITRA T, et al. REVAMP: A systematic framework for heterogeneous CGRA realization[C]. Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 2022: 918–932. doi: 10.1145/3503222.3507772.
    [8]
    JOARDAR B K, KIM R G, DOPPA J R, et al. Learning-based application-agnostic 3D NoC design for heterogeneous manycore systems[J]. IEEE Transactions on Computers, 2019, 68(6): 852–866. doi: 10.1109/TC.2018.2889053.
    [9]
    QI Sirui, LI Yingheng, PASRICHA S, et al. MOELA: A multi-objective evolutionary/learning design space exploration framework for 3D heterogeneous manycore platforms[C]. 2023 Design, Automation & Test in Europe Conference & Exhibition, Antwerp, Belgium, 2023: 1–6. doi: 10.23919/DATE56975.2023.10137276.
    [10]
    KIM R G, DOPPA J R, and PANDE P P. Machine learning for design space exploration and optimization of manycore systems[C]. 2018 IEEE/ACM International Conference on Computer-Aided Design, San Diego, USA, 2018: 1–6. doi: 10.1145/3240765.3243483.
    [11]
    LOPES A S B and PEREIRA M M. A machine learning approach to accelerating DSE of reconfigurable accelerator systems[C]. 2020 33rd Symposium on Integrated Circuits and Systems Design, Campinas, Brazil, 2020: 1–6. doi: 10.1109/SBCCI50935.2020.9189899.
    [12]
    LI Jingyuan, QIU Yunhui, ZHU Guowei, et al. THRAM: A template-based heterogeneous CGRA modeling framework supporting fast DSE[C]. 2023 IEEE International Symposium on Circuits and Systems, Monterey, USA, 2023: 1–5. doi: 10.1109/ISCAS46773.2023.10182204.
    [13]
    PENG Bingbing, SUN Shaoyang, DAI Yuan, et al. PRAD: A Bayesian optimization-based DSE framework for parameterized reconfigurable architecture design[C]. 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines, Marina Del Rey, USA, 2023: 226–226. doi: 10.1109/FCCM57271.2023.00054.
    [14]
    KUANG Huizhen, ZHENG Su, and WANG Lingli. Automated design space exploration of coarse-grained reconfigurable architecture via Bayesian optimization[C]. 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology, Nangjing, China, 2022: 1–3. doi: 10.1109/ICSICT55466.2022.9963336.
    [15]
    DAI Yuan, LI Jingyuan, ZHU Qilong, et al. HETA: A heterogeneous temporal CGRA modeling and design space exploration via Bayesian optimization[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2024, 32(3): 505–518. doi: 10.1109/TVLSI.2023.3344536.
    [16]
    BAI Chen, SUN Qi, ZHAI Jianwang, et al. BOOM-Explorer: RISC-V BOOM microarchitecture design space exploration framework[C]. 2021 IEEE/ACM International Conference on Computer Aided Design, Munich, Germany, 2021: 1–9. doi: 10.1109/ICCAD51958.2021.9643455.
    [17]
    LI Jingyuan, HU Yihan, DAI Yuan, et al. AUGER: A multi-objective design space exploration framework for CGRAs[C]. 2023 International Conference on Field Programmable Technology, Yokohama, Japan, 2023: 88–95. doi: 10.1109/ICFPT59805.2023.00015.
    [18]
    MENG Pingfan, ALTHOFF A, GAUTIER Q, et al. Adaptive threshold non-Pareto elimination: Re-thinking machine learning for system level design space exploration on FPGAs[C]. 2016 Design, Automation & Test in Europe Conference & Exhibition, Dresden, Germany, 2016: 918–923.
    [19]
    KIM Y, MAHAPATRA R N, and CHOI K. Design space exploration for efficient resource utilization in coarse-grained reconfigurable architecture[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010, 18(10): 1471–1482. doi: 10.1109/TVLSI.2009.2025280.
    [20]
    CHEN Sichao, MAO Yiqing, DAI Yuan, et al. FCE: A fast CGRA architecture exploration framework[C]. 2024 IEEE 17th International Conference on Solid-State & Integrated Circuit Technology, Zhuhai, China, 2024: 1–3. doi: 10.1109/ICSICT62049.2024.10832017.
    [21]
    王铎, 刘景磊, 严明玉, 等. 面向处理器微架构设计空间探索的加速方法综述[J]. 计算机研究与发展, 2025, 62(1): 22–57. doi: 10.7544/issn1000-1239.202330348.

    WANG Duo, LIU Jinglei, YAN Mingyu, et al. Acceleration methods for processor microarchitecture design space exploration: A survey[J]. Journal of Computer Research and Development, 2025, 62(1): 22–57. doi: 10.7544/issn1000-1239.202330348.
  • 加载中

Catalog

    通讯作者: 陈斌, bchen63@163.com
    • 1. 

      沈阳化工大学材料科学与工程学院 沈阳 110142

    1. 本站搜索
    2. 百度学术搜索
    3. 万方数据库搜索
    4. CNKI搜索

    Figures(7)  / Tables(8)

    Article Metrics

    Article views (16) PDF downloads(0) Cited by()
    Proportional views
    Related

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return