A Novel Adaptive Optimization Strategy for High-Performance CPU Clock Trees

FAN Lingyan; ZHANG Zhe; HUANG Cankun; LUO Jianping; LIU Hailuan

doi:10.11999/JEIT240811

Volume 47 Issue 4

Apr. 2025

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FAN Lingyan, ZHANG Zhe, HUANG Cankun, LUO Jianping, LIU Hailuan. A Novel Adaptive Optimization Strategy for High-Performance CPU Clock Trees[J]. Journal of Electronics & Information Technology, 2025, 47(4): 1192-1201. doi: 10.11999/JEIT240811

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FAN Lingyan, ZHANG Zhe, HUANG Cankun, LUO Jianping, LIU Hailuan. A Novel Adaptive Optimization Strategy for High-Performance CPU Clock Trees[J]. Journal of Electronics & Information Technology, 2025, 47(4): 1192-1201. doi: 10.11999/JEIT240811

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A Novel Adaptive Optimization Strategy for High-Performance CPU Clock Trees

doi: 10.11999/JEIT240811 cstr: 32379.14.JEIT240811

1.
Microelectronics Research Institute, Hangzhou Dianzi University, Hangzhou 310018, China
2.
Shanghai ESWIN Computing Technology Co., Ltd. Shanghai 200131, China

Funds: The National Natural Science Foundation of China (U22A2071), The National Key Research and Development Program (GG20210104)

Received Date: 2024-09-23
Rev Recd Date: 2025-03-10

Available Online: 2025-03-19

Publish Date: 2025-04-10

Abstract

Abstract

Objective With continuous advancements in Integrated Circuit (IC) process technology, chip integration levels have steadily increased, driving higher market demands for performance. In the era of intelligence and digitalization, an inherent challenge arises: as the number of logic gates increases, both main frequency and power consumption rise, imposing stricter requirements on digital IC designers. Although existing Electronic Design Automation (EDA) tools optimize timing using useful skew in clock trees, this technique has notable limitations. To address this issue, a novel adaptive full-flow clock tree timing violation correction method is proposed. This method corrects timing violations unresolved by conventional flows while reducing power consumption and improving performance, meeting the market’s dual demands for high-performance and low-power chips. Methods The ADaptive Full Flow (ADFF) clock tree optimization method is based on the RISC-V CPU architecture. As an open-source architecture, RISC-V offers openness and flexibility, making it widely used in high-performance, low-power processor design. The method exploits imbalances in key path logic depth to enhance optimization. Useful skew is introduced to adjust logic delay distribution, improving overall performance. Timing feedback is incorporated at multiple stages, ultimately forming a joint optimization strategy for power consumption and timing, which enhances clock tree quality and reduces chip load. The method integrates feedback optimization during both the Clock Tree Synthesis (CTS) and routing stages. In the CTS stage, timing paths are traversed to gather feedback, which is then returned to the pre-CTS stage for early intervention. Adaptive iteration accurately identifies critical paths and resolves setup time violations. In the routing stage, targeted strategies address hold time violations, and the merging method reduces power consumption while optimizing timing correction. This enables full-flow correction of clock tree timing violations while improving power efficiency. Results and Discussions The ADFF clock tree optimization strategy is implemented using Synopsys IC Compiler II for layout and routing, establishing an adaptive full-flow framework for correcting clock tree timing violations (Fig. 5). For setup time violations in the reg2reg group, a loop iteration algorithm dynamically adjusts path delays, updating CTS guidance files to iteratively optimize critical path timing (Fig. 6). Using the ADFF method, total timing violations are nearly eliminated, achieving a 55.6% efficiency improvement over the built-in auto useful skew function (Table 2). For hold time violations in the reg2mem group (Figs. 9 and 10), 125 buffers are inserted. Across 50 critical paths, the total timing margin improves significantly, reducing the worst slack from –362.2 ns to near zero (Table 3). To further optimize timing, when a clock signal is transmitted to two physically close registers, and buffers in the final clock path stage are used for timing correction, a merging plan consolidates multiple register buffers into a single delay unit (Fig. 11). Through a rigorous filtering mechanism in the script language, nearly 700 clock delay units are reduced while maintaining timing integrity. Additionally, clock network nets are reduced (Table 4), improving clock tree quality, achieving timing convergence, and enhancing overall design efficiency. Conclusions This paper proposes a novel ADFF clock tree optimization strategy that integrates loop iteration adjustment with IC Compiler II, leveraging useful skew for adaptive full-flow automatic correction of setup and hold time violations. The method extends the traditional concept and has demonstrated significant results on a high-performance RISC-V-based CPU, achieving a main clock frequency of 800 MHz. Compared to conventional timing optimization methods, this strategy resolves timing violations that standard layout and routing processes cannot address, significantly improving timing convergence. Through joint optimization of power consumption and timing, the method reduces the cost and power overhead associated with useful skew optimization and is applicable to CPU pipelines, providing a valuable reference for chip design. Future research may refine filtering conditions, optimize script traversal statements, and incorporate mainstream tool techniques to improve path selection efficiency while minimizing runtime overhead in large designs. Additionally, further refinement of the mathematical model could help identify more suitable targets for power optimization, improving overall performance.
- Clock tree,
- Useful skew,
- Adaptation,
- Timing violation,
- Joint optimization

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References(17)

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